reference, declaration → definition definition → references, declarations, derived classes, virtual overrides reference to multiple definitions → definitions unreferenced |
2486 case MCK_MemOffsetSimmPtr: 3739 case MCK_MemOffsetSimmPtr: { 4713 case MCK_MemOffsetSimmPtr: return "MCK_MemOffsetSimmPtr"; 6795 { 5427 /* lb */, Mips::LB, Convert__GPR32AsmReg1_0__MemOffsetSimmPtr2_1, AMFBS_HasStdEnc_NotInMicroMips, { MCK_GPR32AsmReg, MCK_MemOffsetSimmPtr }, }, 6800 { 5434 /* lbu */, Mips::LBu, Convert__GPR32AsmReg1_0__MemOffsetSimmPtr2_1, AMFBS_HasStdEnc_NotInMicroMips, { MCK_GPR32AsmReg, MCK_MemOffsetSimmPtr }, }, 6807 { 5454 /* ld */, Mips::LD, Convert__GPR64AsmReg1_0__MemOffsetSimmPtr2_1, AMFBS_HasStdEnc_HasMips3_NotInMicroMips, { MCK_GPR64AsmReg, MCK_MemOffsetSimmPtr }, }, 6829 { 5535 /* lh */, Mips::LH, Convert__GPR32AsmReg1_0__MemOffsetSimmPtr2_1, AMFBS_HasStdEnc_NotInMicroMips, { MCK_GPR32AsmReg, MCK_MemOffsetSimmPtr }, }, 6830 { 5535 /* lh */, Mips::LH_MM, Convert__GPR32AsmReg1_0__MemOffsetSimmPtr2_1, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_MemOffsetSimmPtr }, }, 6833 { 5542 /* lhu */, Mips::LHu, Convert__GPR32AsmReg1_0__MemOffsetSimmPtr2_1, AMFBS_HasStdEnc_NotInMicroMips, { MCK_GPR32AsmReg, MCK_MemOffsetSimmPtr }, }, 6834 { 5542 /* lhu */, Mips::LHu_MM, Convert__GPR32AsmReg1_0__MemOffsetSimmPtr2_1, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_MemOffsetSimmPtr }, }, 6856 { 5582 /* lld */, Mips::LLD, Convert__GPR64AsmReg1_0__MemOffsetSimmPtr2_1, AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotInMicroMips, { MCK_GPR64AsmReg, MCK_MemOffsetSimmPtr }, }, 6857 { 5582 /* lld */, Mips::LLD_R6, Convert__GPR64AsmReg1_0__MemOffsetSimmPtr2_1, AMFBS_HasStdEnc_HasMips64r6_NotInMicroMips, { MCK_GPR64AsmReg, MCK_MemOffsetSimmPtr }, }, 7517 { 7931 /* sd */, Mips::SD, Convert__GPR64AsmReg1_0__MemOffsetSimmPtr2_1, AMFBS_HasStdEnc_HasMips3_NotInMicroMips, { MCK_GPR64AsmReg, MCK_MemOffsetSimmPtr }, }, 10065 { 5427 /* lb */, 2 /* 1 */, MCK_MemOffsetSimmPtr, AMFBS_HasStdEnc_NotInMicroMips }, 10075 { 5434 /* lbu */, 2 /* 1 */, MCK_MemOffsetSimmPtr, AMFBS_HasStdEnc_NotInMicroMips }, 10087 { 5454 /* ld */, 2 /* 1 */, MCK_MemOffsetSimmPtr, AMFBS_HasStdEnc_HasMips3_NotInMicroMips }, 10127 { 5535 /* lh */, 2 /* 1 */, MCK_MemOffsetSimmPtr, AMFBS_HasStdEnc_NotInMicroMips }, 10129 { 5535 /* lh */, 2 /* 1 */, MCK_MemOffsetSimmPtr, AMFBS_InMicroMips }, 10135 { 5542 /* lhu */, 2 /* 1 */, MCK_MemOffsetSimmPtr, AMFBS_HasStdEnc_NotInMicroMips }, 10137 { 5542 /* lhu */, 2 /* 1 */, MCK_MemOffsetSimmPtr, AMFBS_InMicroMips }, 10167 { 5582 /* lld */, 2 /* 1 */, MCK_MemOffsetSimmPtr, AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotInMicroMips }, 10169 { 5582 /* lld */, 2 /* 1 */, MCK_MemOffsetSimmPtr, AMFBS_HasStdEnc_HasMips64r6_NotInMicroMips }, 11013 { 7931 /* sd */, 2 /* 1 */, MCK_MemOffsetSimmPtr, AMFBS_HasStdEnc_HasMips3_NotInMicroMips }, 11656 case MCK_MemOffsetSimmPtr: