reference, declaration → definition definition → references, declarations, derived classes, virtual overrides reference to multiple definitions → definitions unreferenced |
2480 case MCK_MemOffsetSimm16: 3721 case MCK_MemOffsetSimm16: { 4711 case MCK_MemOffsetSimm16: return "MCK_MemOffsetSimm16"; 6786 { 5411 /* l.d */, Mips::LDC1, Convert__AFGR64AsmReg1_0__MemOffsetSimm162_1, AMFBS_HasStdEnc_NotFP64bit_HasMips2_IsNotSoftFloat, { MCK_AFGR64AsmReg, MCK_MemOffsetSimm16 }, }, 6787 { 5411 /* l.d */, Mips::LDC164, Convert__FGR64AsmReg1_0__MemOffsetSimm162_1, AMFBS_HasStdEnc_IsFP64bit_HasMips2_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_MemOffsetSimm16 }, }, 6788 { 5415 /* l.s */, Mips::LWC1, Convert__FGR32AsmReg1_0__MemOffsetSimm162_1, AMFBS_HasStdEnc_HasMips2_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_MemOffsetSimm16 }, }, 6793 { 5427 /* lb */, Mips::LB_MMR6, Convert__GPR32AsmReg1_0__MemOffsetSimm162_1, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_MemOffsetSimm16 }, }, 6794 { 5427 /* lb */, Mips::LB_MM, Convert__GPR32AsmReg1_0__MemOffsetSimm162_1, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_MemOffsetSimm16 }, }, 6798 { 5434 /* lbu */, Mips::LBU_MMR6, Convert__GPR32AsmReg1_0__MemOffsetSimm162_1, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_MemOffsetSimm16 }, }, 6799 { 5434 /* lbu */, Mips::LBu_MM, Convert__GPR32AsmReg1_0__MemOffsetSimm162_1, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_MemOffsetSimm16 }, }, 6806 { 5454 /* ld */, Mips::LDMacro, Convert__GPR32AsmReg1_0__MemOffsetSimm162_1, AMFBS_HasStdEnc_NotMips3, { MCK_GPR32AsmReg, MCK_MemOffsetSimm16 }, }, 6812 { 5477 /* ldc1 */, Mips::LDC1, Convert__AFGR64AsmReg1_0__MemOffsetSimm162_1, AMFBS_HasStdEnc_NotFP64bit_HasMips2_IsNotSoftFloat_NotInMicroMips, { MCK_AFGR64AsmReg, MCK_MemOffsetSimm16 }, }, 6813 { 5477 /* ldc1 */, Mips::LDC1_MM, Convert__AFGR64AsmReg1_0__MemOffsetSimm162_1, AMFBS_InMicroMips_NotFP64bit_IsNotSoftFloat, { MCK_AFGR64AsmReg, MCK_MemOffsetSimm16 }, }, 6814 { 5477 /* ldc1 */, Mips::LDC164, Convert__FGR64AsmReg1_0__MemOffsetSimm162_1, AMFBS_HasStdEnc_IsFP64bit_HasMips2_IsNotSoftFloat_NotInMicroMips, { MCK_FGR64AsmReg, MCK_MemOffsetSimm16 }, }, 6815 { 5477 /* ldc1 */, Mips::LDC1_D64_MMR6, Convert__FGR64AsmReg1_0__MemOffsetSimm162_1, AMFBS_InMicroMips_IsFP64bit_HasMips32r6_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_MemOffsetSimm16 }, }, 6818 { 5482 /* ldc2 */, Mips::LDC2, Convert__COP2AsmReg1_0__MemOffsetSimm162_1, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips, { MCK_COP2AsmReg, MCK_MemOffsetSimm16 }, }, 6880 { 5612 /* lwc1 */, Mips::LWC1, Convert__FGR32AsmReg1_0__MemOffsetSimm162_1, AMFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips, { MCK_FGR32AsmReg, MCK_MemOffsetSimm16 }, }, 6881 { 5612 /* lwc1 */, Mips::LWC1_MM, Convert__FGR32AsmReg1_0__MemOffsetSimm162_1, AMFBS_InMicroMips_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_MemOffsetSimm16 }, }, 6884 { 5617 /* lwc2 */, Mips::LWC2, Convert__COP2AsmReg1_0__MemOffsetSimm162_1, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips, { MCK_COP2AsmReg, MCK_MemOffsetSimm16 }, }, 7485 { 7836 /* s.d */, Mips::SDC1, Convert__AFGR64AsmReg1_0__MemOffsetSimm162_1, AMFBS_HasStdEnc_NotFP64bit_HasMips2_IsNotSoftFloat, { MCK_AFGR64AsmReg, MCK_MemOffsetSimm16 }, }, 7486 { 7836 /* s.d */, Mips::SDC1_M1, Convert__AFGR64AsmReg1_0__MemOffsetSimm162_1, AMFBS_HasStdEnc_NotFP64bit_IsNotSoftFloat, { MCK_AFGR64AsmReg, MCK_MemOffsetSimm16 }, }, 7487 { 7836 /* s.d */, Mips::SDC1_M1, Convert__AFGR64AsmReg1_0__MemOffsetSimm162_1, AMFBS_HasStdEnc_NotFP64bit_IsNotSoftFloat, { MCK_AFGR64AsmReg, MCK_MemOffsetSimm16 }, }, 7488 { 7836 /* s.d */, Mips::SDC164, Convert__FGR64AsmReg1_0__MemOffsetSimm162_1, AMFBS_HasStdEnc_IsFP64bit_HasMips2_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_MemOffsetSimm16 }, }, 7489 { 7840 /* s.s */, Mips::SWC1, Convert__FGR32AsmReg1_0__MemOffsetSimm162_1, AMFBS_HasStdEnc_HasMips2_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_MemOffsetSimm16 }, }, 7516 { 7931 /* sd */, Mips::SDMacro, Convert__GPR32AsmReg1_0__MemOffsetSimm162_1, AMFBS_HasStdEnc_NotMips3, { MCK_GPR32AsmReg, MCK_MemOffsetSimm16 }, }, 7527 { 7948 /* sdc1 */, Mips::SDC1, Convert__AFGR64AsmReg1_0__MemOffsetSimm162_1, AMFBS_HasStdEnc_NotFP64bit_HasMips2_IsNotSoftFloat_NotInMicroMips, { MCK_AFGR64AsmReg, MCK_MemOffsetSimm16 }, }, 7528 { 7948 /* sdc1 */, Mips::SDC1_MM, Convert__AFGR64AsmReg1_0__MemOffsetSimm162_1, AMFBS_InMicroMips_NotFP64bit_IsNotSoftFloat, { MCK_AFGR64AsmReg, MCK_MemOffsetSimm16 }, }, 7529 { 7948 /* sdc1 */, Mips::SDC164, Convert__FGR64AsmReg1_0__MemOffsetSimm162_1, AMFBS_HasStdEnc_IsFP64bit_HasMips2_IsNotSoftFloat_NotInMicroMips, { MCK_FGR64AsmReg, MCK_MemOffsetSimm16 }, }, 7530 { 7948 /* sdc1 */, Mips::SDC1_D64_MMR6, Convert__FGR64AsmReg1_0__MemOffsetSimm162_1, AMFBS_InMicroMips_IsFP64bit_HasMips32r6_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_MemOffsetSimm16 }, }, 7533 { 7953 /* sdc2 */, Mips::SDC2, Convert__COP2AsmReg1_0__MemOffsetSimm162_1, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips, { MCK_COP2AsmReg, MCK_MemOffsetSimm16 }, }, 7900 { 9214 /* swc1 */, Mips::SWC1, Convert__FGR32AsmReg1_0__MemOffsetSimm162_1, AMFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips, { MCK_FGR32AsmReg, MCK_MemOffsetSimm16 }, }, 7901 { 9214 /* swc1 */, Mips::SWC1_MM, Convert__FGR32AsmReg1_0__MemOffsetSimm162_1, AMFBS_InMicroMips_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_MemOffsetSimm16 }, }, 7904 { 9219 /* swc2 */, Mips::SWC2, Convert__COP2AsmReg1_0__MemOffsetSimm162_1, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips, { MCK_COP2AsmReg, MCK_MemOffsetSimm16 }, }, 7930 { 9287 /* synci */, Mips::SYNCI, Convert__MemOffsetSimm162_0, AMFBS_HasStdEnc_HasMips32r2_NotInMicroMips, { MCK_MemOffsetSimm16 }, }, 7931 { 9287 /* synci */, Mips::SYNCI_MM, Convert__MemOffsetSimm162_0, AMFBS_InMicroMips_NotMips32r6, { MCK_MemOffsetSimm16 }, }, 7932 { 9287 /* synci */, Mips::SYNCI_MMR6, Convert__MemOffsetSimm162_0, AMFBS_InMicroMips_HasMips32r6, { MCK_MemOffsetSimm16 }, }, 10050 { 5411 /* l.d */, 2 /* 1 */, MCK_MemOffsetSimm16, AMFBS_HasStdEnc_NotFP64bit_HasMips2_IsNotSoftFloat }, 10052 { 5411 /* l.d */, 2 /* 1 */, MCK_MemOffsetSimm16, AMFBS_HasStdEnc_IsFP64bit_HasMips2_IsNotSoftFloat }, 10054 { 5415 /* l.s */, 2 /* 1 */, MCK_MemOffsetSimm16, AMFBS_HasStdEnc_HasMips2_IsNotSoftFloat }, 10061 { 5427 /* lb */, 2 /* 1 */, MCK_MemOffsetSimm16, AMFBS_InMicroMips_HasMips32r6 }, 10063 { 5427 /* lb */, 2 /* 1 */, MCK_MemOffsetSimm16, AMFBS_InMicroMips }, 10071 { 5434 /* lbu */, 2 /* 1 */, MCK_MemOffsetSimm16, AMFBS_InMicroMips_HasMips32r6 }, 10073 { 5434 /* lbu */, 2 /* 1 */, MCK_MemOffsetSimm16, AMFBS_InMicroMips }, 10085 { 5454 /* ld */, 2 /* 1 */, MCK_MemOffsetSimm16, AMFBS_HasStdEnc_NotMips3 }, 10097 { 5477 /* ldc1 */, 2 /* 1 */, MCK_MemOffsetSimm16, AMFBS_HasStdEnc_NotFP64bit_HasMips2_IsNotSoftFloat_NotInMicroMips }, 10099 { 5477 /* ldc1 */, 2 /* 1 */, MCK_MemOffsetSimm16, AMFBS_InMicroMips_NotFP64bit_IsNotSoftFloat }, 10101 { 5477 /* ldc1 */, 2 /* 1 */, MCK_MemOffsetSimm16, AMFBS_HasStdEnc_IsFP64bit_HasMips2_IsNotSoftFloat_NotInMicroMips }, 10103 { 5477 /* ldc1 */, 2 /* 1 */, MCK_MemOffsetSimm16, AMFBS_InMicroMips_IsFP64bit_HasMips32r6_IsNotSoftFloat }, 10109 { 5482 /* ldc2 */, 2 /* 1 */, MCK_MemOffsetSimm16, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips }, 10203 { 5612 /* lwc1 */, 2 /* 1 */, MCK_MemOffsetSimm16, AMFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips }, 10205 { 5612 /* lwc1 */, 2 /* 1 */, MCK_MemOffsetSimm16, AMFBS_InMicroMips_IsNotSoftFloat }, 10211 { 5617 /* lwc2 */, 2 /* 1 */, MCK_MemOffsetSimm16, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips }, 10959 { 7836 /* s.d */, 2 /* 1 */, MCK_MemOffsetSimm16, AMFBS_HasStdEnc_NotFP64bit_HasMips2_IsNotSoftFloat }, 10961 { 7836 /* s.d */, 2 /* 1 */, MCK_MemOffsetSimm16, AMFBS_HasStdEnc_NotFP64bit_IsNotSoftFloat }, 10963 { 7836 /* s.d */, 2 /* 1 */, MCK_MemOffsetSimm16, AMFBS_HasStdEnc_NotFP64bit_IsNotSoftFloat }, 10965 { 7836 /* s.d */, 2 /* 1 */, MCK_MemOffsetSimm16, AMFBS_HasStdEnc_IsFP64bit_HasMips2_IsNotSoftFloat }, 10967 { 7840 /* s.s */, 2 /* 1 */, MCK_MemOffsetSimm16, AMFBS_HasStdEnc_HasMips2_IsNotSoftFloat }, 11011 { 7931 /* sd */, 2 /* 1 */, MCK_MemOffsetSimm16, AMFBS_HasStdEnc_NotMips3 }, 11015 { 7948 /* sdc1 */, 2 /* 1 */, MCK_MemOffsetSimm16, AMFBS_HasStdEnc_NotFP64bit_HasMips2_IsNotSoftFloat_NotInMicroMips }, 11017 { 7948 /* sdc1 */, 2 /* 1 */, MCK_MemOffsetSimm16, AMFBS_InMicroMips_NotFP64bit_IsNotSoftFloat }, 11019 { 7948 /* sdc1 */, 2 /* 1 */, MCK_MemOffsetSimm16, AMFBS_HasStdEnc_IsFP64bit_HasMips2_IsNotSoftFloat_NotInMicroMips }, 11021 { 7948 /* sdc1 */, 2 /* 1 */, MCK_MemOffsetSimm16, AMFBS_InMicroMips_IsFP64bit_HasMips32r6_IsNotSoftFloat }, 11027 { 7953 /* sdc2 */, 2 /* 1 */, MCK_MemOffsetSimm16, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips }, 11412 { 9214 /* swc1 */, 2 /* 1 */, MCK_MemOffsetSimm16, AMFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips }, 11414 { 9214 /* swc1 */, 2 /* 1 */, MCK_MemOffsetSimm16, AMFBS_InMicroMips_IsNotSoftFloat }, 11420 { 9219 /* swc2 */, 2 /* 1 */, MCK_MemOffsetSimm16, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips }, 11459 { 9287 /* synci */, 1 /* 0 */, MCK_MemOffsetSimm16, AMFBS_HasStdEnc_HasMips32r2_NotInMicroMips }, 11460 { 9287 /* synci */, 1 /* 0 */, MCK_MemOffsetSimm16, AMFBS_InMicroMips_NotMips32r6 }, 11461 { 9287 /* synci */, 1 /* 0 */, MCK_MemOffsetSimm16, AMFBS_InMicroMips_HasMips32r6 }, 11652 case MCK_MemOffsetSimm16: