reference, declarationdefinition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced

References

gen/lib/Target/Mips/MipsGenAsmMatcher.inc
 2463     return B == MCK_Mem;
 2466     return B == MCK_Mem;
 2469     return B == MCK_Mem;
 2472     return B == MCK_Mem;
 2475     return B == MCK_Mem;
 2478     return B == MCK_Mem;
 2481     return B == MCK_Mem;
 2484     return B == MCK_Mem;
 2487     return B == MCK_Mem;
 2490     return B == MCK_Mem;
 3755   case MCK_Mem: {
 4715   case MCK_Mem: return "MCK_Mem";
 6042   { 1962 /* cache */, Mips::CACHE, Convert__Mem2_1__ConstantUImm5_01_0, AMFBS_HasStdEnc_HasMips3_32_NotMips32r6_NotMips64r6_NotInMicroMips, { MCK_ConstantUImm5_0, MCK_Mem }, },
 6043   { 1962 /* cache */, Mips::CACHE_MM, Convert__Mem2_1__ConstantUImm5_01_0, AMFBS_InMicroMips_NotMips32r6, { MCK_ConstantUImm5_0, MCK_Mem }, },
 6044   { 1962 /* cache */, Mips::CACHE_MMR6, Convert__Mem2_1__ConstantUImm5_01_0, AMFBS_InMicroMips_HasMips32r6, { MCK_ConstantUImm5_0, MCK_Mem }, },
 6357   { 3314 /* dla */, Mips::LoadAddrReg64, Convert__GPR64AsmReg1_0__Mem2_1, AMFBS_None, { MCK_GPR64AsmReg, MCK_Mem }, },
 6790   { 5419 /* la */, Mips::LoadAddrReg32, Convert__GPR32AsmReg1_0__Mem2_1, AMFBS_None, { MCK_GPR32AsmReg, MCK_Mem }, },
 6797   { 5430 /* lbe */, Mips::LBE_MM, Convert__GPR32AsmReg1_0__Mem2_1, AMFBS_InMicroMips_HasEVA, { MCK_GPR32AsmReg, MCK_Mem }, },
 6803   { 5444 /* lbue */, Mips::LBuE_MM, Convert__GPR32AsmReg1_0__Mem2_1, AMFBS_InMicroMips_HasEVA, { MCK_GPR32AsmReg, MCK_Mem }, },
 6819   { 5487 /* ldc3 */, Mips::LDC3, Convert__COP3AsmReg1_0__Mem2_1, AMFBS_HasStdEnc_HasMips2_NotCnMips_NotInMicroMips, { MCK_COP3AsmReg, MCK_Mem }, },
 6824   { 5516 /* ldl */, Mips::LDL, Convert__GPR64AsmReg1_0__Mem2_1__Tie0_1_1, AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6, { MCK_GPR64AsmReg, MCK_Mem }, },
 6826   { 5525 /* ldr */, Mips::LDR, Convert__GPR64AsmReg1_0__Mem2_1__Tie0_1_1, AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6, { MCK_GPR64AsmReg, MCK_Mem }, },
 6853   { 5579 /* ll */, Mips::LL, Convert__GPR32AsmReg1_0__Mem2_1, AMFBS_HasStdEnc_IsPTR32bit_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips, { MCK_GPR32AsmReg, MCK_Mem }, },
 6854   { 5579 /* ll */, Mips::LL64, Convert__GPR32AsmReg1_0__Mem2_1, AMFBS_HasStdEnc_IsPTR64bit_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips, { MCK_GPR32AsmReg, MCK_Mem }, },
 6855   { 5579 /* ll */, Mips::LL_MM, Convert__GPR32AsmReg1_0__Mem2_1, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32AsmReg, MCK_Mem }, },
 6871   { 5604 /* lw */, Mips::LW, Convert__GPR32AsmReg1_0__Mem2_1, AMFBS_HasStdEnc_NotInMicroMips, { MCK_GPR32AsmReg, MCK_Mem }, },
 6872   { 5604 /* lw */, Mips::LWDSP, Convert__GPR32AsmReg1_0__Mem2_1, AMFBS_NotInMips16Mode_HasDSP, { MCK_GPR32AsmReg, MCK_Mem }, },
 6873   { 5604 /* lw */, Mips::LWDSP_MM, Convert__GPR32AsmReg1_0__Mem2_1, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_Mem }, },
 6874   { 5604 /* lw */, Mips::LW_MMR6, Convert__GPR32AsmReg1_0__Mem2_1, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_Mem }, },
 6875   { 5604 /* lw */, Mips::LW_MM, Convert__GPR32AsmReg1_0__Mem2_1, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_Mem }, },
 6885   { 5622 /* lwc3 */, Mips::LWC3, Convert__COP3AsmReg1_0__Mem2_1, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotCnMips_NotInMicroMips, { MCK_COP3AsmReg, MCK_Mem }, },
 6888   { 5631 /* lwl */, Mips::LWL, Convert__GPR32AsmReg1_0__Mem2_1__Tie0_1_1, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips, { MCK_GPR32AsmReg, MCK_Mem }, },
 6889   { 5631 /* lwl */, Mips::LWL_MM, Convert__GPR32AsmReg1_0__Mem2_1__Tie0_1_1, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32AsmReg, MCK_Mem }, },
 6892   { 5640 /* lwm */, Mips::LWM_MM, Convert__RegList1_0__Mem2_1, AMFBS_InMicroMips, { MCK_RegList, MCK_Mem }, },
 6895   { 5650 /* lwm32 */, Mips::LWM32_MM, Convert__RegList1_0__Mem2_1, AMFBS_InMicroMips, { MCK_RegList, MCK_Mem }, },
 6899   { 5665 /* lwr */, Mips::LWR, Convert__GPR32AsmReg1_0__Mem2_1__Tie0_1_1, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips, { MCK_GPR32AsmReg, MCK_Mem }, },
 6900   { 5665 /* lwr */, Mips::LWR_MM, Convert__GPR32AsmReg1_0__Mem2_1__Tie0_1_1, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32AsmReg, MCK_Mem }, },
 6904   { 5674 /* lwu */, Mips::LWu, Convert__GPR64AsmReg1_0__Mem2_1, AMFBS_HasStdEnc_HasMips3_NotInMicroMips, { MCK_GPR64AsmReg, MCK_Mem }, },
 7407   { 7633 /* pref */, Mips::PREF, Convert__Mem2_1__ConstantUImm5_01_0, AMFBS_HasStdEnc_HasMips3_32_NotMips32r6_NotMips64r6_NotInMicroMips, { MCK_ConstantUImm5_0, MCK_Mem }, },
 7408   { 7633 /* pref */, Mips::PREF_MM, Convert__Mem2_1__ConstantUImm5_01_0, AMFBS_InMicroMips_NotMips32r6, { MCK_ConstantUImm5_0, MCK_Mem }, },
 7409   { 7633 /* pref */, Mips::PREF_MMR6, Convert__Mem2_1__ConstantUImm5_01_0, AMFBS_InMicroMips_HasMips32r6, { MCK_ConstantUImm5_0, MCK_Mem }, },
 7498   { 7908 /* sb */, Mips::SB, Convert__GPR32AsmReg1_0__Mem2_1, AMFBS_HasStdEnc_NotInMicroMips, { MCK_GPR32AsmReg, MCK_Mem }, },
 7499   { 7908 /* sb */, Mips::SB_MMR6, Convert__GPR32AsmReg1_0__Mem2_1, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_Mem }, },
 7500   { 7908 /* sb */, Mips::SB_MM, Convert__GPR32AsmReg1_0__Mem2_1, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_Mem }, },
 7509   { 7920 /* sc */, Mips::SC, Convert__GPR32AsmReg1_0__Tie0_1_1__Mem2_1, AMFBS_HasStdEnc_IsPTR32bit_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips, { MCK_GPR32AsmReg, MCK_Mem }, },
 7510   { 7920 /* sc */, Mips::SC64, Convert__GPR32AsmReg1_0__Tie0_1_1__Mem2_1, AMFBS_HasStdEnc_IsPTR64bit_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips, { MCK_GPR32AsmReg, MCK_Mem }, },
 7511   { 7920 /* sc */, Mips::SC_MM, Convert__GPR32AsmReg1_0__Tie0_1_1__Mem2_1, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32AsmReg, MCK_Mem }, },
 7513   { 7923 /* scd */, Mips::SCD, Convert__GPR64AsmReg1_0__Tie0_1_1__Mem2_1, AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6, { MCK_GPR64AsmReg, MCK_Mem }, },
 7534   { 7958 /* sdc3 */, Mips::SDC3, Convert__COP3AsmReg1_0__Mem2_1, AMFBS_HasStdEnc_HasMips2_NotCnMips_NotInMicroMips, { MCK_COP3AsmReg, MCK_Mem }, },
 7535   { 7963 /* sdl */, Mips::SDL, Convert__GPR64AsmReg1_0__Mem2_1, AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6, { MCK_GPR64AsmReg, MCK_Mem }, },
 7536   { 7967 /* sdr */, Mips::SDR, Convert__GPR64AsmReg1_0__Mem2_1, AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6, { MCK_GPR64AsmReg, MCK_Mem }, },
 7603   { 8074 /* sh */, Mips::SH, Convert__GPR32AsmReg1_0__Mem2_1, AMFBS_HasStdEnc_NotInMicroMips, { MCK_GPR32AsmReg, MCK_Mem }, },
 7604   { 8074 /* sh */, Mips::SH_MMR6, Convert__GPR32AsmReg1_0__Mem2_1, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_Mem }, },
 7605   { 8074 /* sh */, Mips::SH_MM, Convert__GPR32AsmReg1_0__Mem2_1, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_Mem }, },
 7891   { 9206 /* sw */, Mips::SW, Convert__GPR32AsmReg1_0__Mem2_1, AMFBS_HasStdEnc_NotInMicroMips, { MCK_GPR32AsmReg, MCK_Mem }, },
 7892   { 9206 /* sw */, Mips::SWDSP, Convert__GPR32AsmReg1_0__Mem2_1, AMFBS_NotInMips16Mode_HasDSP, { MCK_GPR32AsmReg, MCK_Mem }, },
 7893   { 9206 /* sw */, Mips::SWDSP_MM, Convert__GPR32AsmReg1_0__Mem2_1, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_Mem }, },
 7894   { 9206 /* sw */, Mips::SW_MMR6, Convert__GPR32AsmReg1_0__Mem2_1, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_Mem }, },
 7895   { 9206 /* sw */, Mips::SW_MM, Convert__GPR32AsmReg1_0__Mem2_1, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_Mem }, },
 7905   { 9224 /* swc3 */, Mips::SWC3, Convert__COP3AsmReg1_0__Mem2_1, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotCnMips_NotInMicroMips, { MCK_COP3AsmReg, MCK_Mem }, },
 7908   { 9233 /* swl */, Mips::SWL, Convert__GPR32AsmReg1_0__Mem2_1, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips, { MCK_GPR32AsmReg, MCK_Mem }, },
 7909   { 9233 /* swl */, Mips::SWL_MM, Convert__GPR32AsmReg1_0__Mem2_1, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32AsmReg, MCK_Mem }, },
 7912   { 9242 /* swm */, Mips::SWM_MM, Convert__RegList1_0__Mem2_1, AMFBS_InMicroMips, { MCK_RegList, MCK_Mem }, },
 7915   { 9252 /* swm32 */, Mips::SWM32_MM, Convert__RegList1_0__Mem2_1, AMFBS_InMicroMips, { MCK_RegList, MCK_Mem }, },
 7917   { 9262 /* swr */, Mips::SWR, Convert__GPR32AsmReg1_0__Mem2_1, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips, { MCK_GPR32AsmReg, MCK_Mem }, },
 7918   { 9262 /* swr */, Mips::SWR_MM, Convert__GPR32AsmReg1_0__Mem2_1, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32AsmReg, MCK_Mem }, },
 8015   { 9509 /* ulh */, Mips::Ulh, Convert__GPR32AsmReg1_0__Mem2_1, AMFBS_None, { MCK_GPR32AsmReg, MCK_Mem }, },
 8016   { 9513 /* ulhu */, Mips::Ulhu, Convert__GPR32AsmReg1_0__Mem2_1, AMFBS_None, { MCK_GPR32AsmReg, MCK_Mem }, },
 8017   { 9518 /* ulw */, Mips::Ulw, Convert__GPR32AsmReg1_0__Mem2_1, AMFBS_None, { MCK_GPR32AsmReg, MCK_Mem }, },
 8018   { 9522 /* ush */, Mips::Ush, Convert__GPR32AsmReg1_0__Mem2_1, AMFBS_None, { MCK_GPR32AsmReg, MCK_Mem }, },
 8019   { 9526 /* usw */, Mips::Usw, Convert__GPR32AsmReg1_0__Mem2_1, AMFBS_None, { MCK_GPR32AsmReg, MCK_Mem }, },
 9158   { 1962 /* cache */, 2 /* 1 */, MCK_Mem, AMFBS_HasStdEnc_HasMips3_32_NotMips32r6_NotMips64r6_NotInMicroMips },
 9159   { 1962 /* cache */, 2 /* 1 */, MCK_Mem, AMFBS_InMicroMips_NotMips32r6 },
 9160   { 1962 /* cache */, 2 /* 1 */, MCK_Mem, AMFBS_InMicroMips_HasMips32r6 },
 9547   { 3314 /* dla */, 2 /* 1 */, MCK_Mem, AMFBS_None },
10057   { 5419 /* la */, 2 /* 1 */, MCK_Mem, AMFBS_None },
10069   { 5430 /* lbe */, 2 /* 1 */, MCK_Mem, AMFBS_InMicroMips_HasEVA },
10081   { 5444 /* lbue */, 2 /* 1 */, MCK_Mem, AMFBS_InMicroMips_HasEVA },
10111   { 5487 /* ldc3 */, 2 /* 1 */, MCK_Mem, AMFBS_HasStdEnc_HasMips2_NotCnMips_NotInMicroMips },
10117   { 5516 /* ldl */, 2 /* 1 */, MCK_Mem, AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6 },
10121   { 5525 /* ldr */, 2 /* 1 */, MCK_Mem, AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6 },
10161   { 5579 /* ll */, 2 /* 1 */, MCK_Mem, AMFBS_HasStdEnc_IsPTR32bit_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips },
10163   { 5579 /* ll */, 2 /* 1 */, MCK_Mem, AMFBS_HasStdEnc_IsPTR64bit_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips },
10165   { 5579 /* ll */, 2 /* 1 */, MCK_Mem, AMFBS_InMicroMips_NotMips32r6 },
10189   { 5604 /* lw */, 2 /* 1 */, MCK_Mem, AMFBS_HasStdEnc_NotInMicroMips },
10191   { 5604 /* lw */, 2 /* 1 */, MCK_Mem, AMFBS_NotInMips16Mode_HasDSP },
10193   { 5604 /* lw */, 2 /* 1 */, MCK_Mem, AMFBS_InMicroMips_HasDSP },
10195   { 5604 /* lw */, 2 /* 1 */, MCK_Mem, AMFBS_InMicroMips_HasMips32r6 },
10197   { 5604 /* lw */, 2 /* 1 */, MCK_Mem, AMFBS_InMicroMips },
10213   { 5622 /* lwc3 */, 2 /* 1 */, MCK_Mem, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotCnMips_NotInMicroMips },
10219   { 5631 /* lwl */, 2 /* 1 */, MCK_Mem, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips },
10221   { 5631 /* lwl */, 2 /* 1 */, MCK_Mem, AMFBS_InMicroMips_NotMips32r6 },
10226   { 5640 /* lwm */, 2 /* 1 */, MCK_Mem, AMFBS_InMicroMips },
10232   { 5650 /* lwm32 */, 2 /* 1 */, MCK_Mem, AMFBS_InMicroMips },
10239   { 5665 /* lwr */, 2 /* 1 */, MCK_Mem, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips },
10241   { 5665 /* lwr */, 2 /* 1 */, MCK_Mem, AMFBS_InMicroMips_NotMips32r6 },
10249   { 5674 /* lwu */, 2 /* 1 */, MCK_Mem, AMFBS_HasStdEnc_HasMips3_NotInMicroMips },
10868   { 7633 /* pref */, 2 /* 1 */, MCK_Mem, AMFBS_HasStdEnc_HasMips3_32_NotMips32r6_NotMips64r6_NotInMicroMips },
10869   { 7633 /* pref */, 2 /* 1 */, MCK_Mem, AMFBS_InMicroMips_NotMips32r6 },
10870   { 7633 /* pref */, 2 /* 1 */, MCK_Mem, AMFBS_InMicroMips_HasMips32r6 },
10977   { 7908 /* sb */, 2 /* 1 */, MCK_Mem, AMFBS_HasStdEnc_NotInMicroMips },
10979   { 7908 /* sb */, 2 /* 1 */, MCK_Mem, AMFBS_InMicroMips_HasMips32r6 },
10981   { 7908 /* sb */, 2 /* 1 */, MCK_Mem, AMFBS_InMicroMips },
10997   { 7920 /* sc */, 2 /* 1 */, MCK_Mem, AMFBS_HasStdEnc_IsPTR32bit_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips },
10999   { 7920 /* sc */, 2 /* 1 */, MCK_Mem, AMFBS_HasStdEnc_IsPTR64bit_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips },
11001   { 7920 /* sc */, 2 /* 1 */, MCK_Mem, AMFBS_InMicroMips_NotMips32r6 },
11005   { 7923 /* scd */, 2 /* 1 */, MCK_Mem, AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6 },
11029   { 7958 /* sdc3 */, 2 /* 1 */, MCK_Mem, AMFBS_HasStdEnc_HasMips2_NotCnMips_NotInMicroMips },
11031   { 7963 /* sdl */, 2 /* 1 */, MCK_Mem, AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6 },
11033   { 7967 /* sdr */, 2 /* 1 */, MCK_Mem, AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6 },
11101   { 8074 /* sh */, 2 /* 1 */, MCK_Mem, AMFBS_HasStdEnc_NotInMicroMips },
11103   { 8074 /* sh */, 2 /* 1 */, MCK_Mem, AMFBS_InMicroMips_HasMips32r6 },
11105   { 8074 /* sh */, 2 /* 1 */, MCK_Mem, AMFBS_InMicroMips },
11398   { 9206 /* sw */, 2 /* 1 */, MCK_Mem, AMFBS_HasStdEnc_NotInMicroMips },
11400   { 9206 /* sw */, 2 /* 1 */, MCK_Mem, AMFBS_NotInMips16Mode_HasDSP },
11402   { 9206 /* sw */, 2 /* 1 */, MCK_Mem, AMFBS_InMicroMips_HasDSP },
11404   { 9206 /* sw */, 2 /* 1 */, MCK_Mem, AMFBS_InMicroMips_HasMips32r6 },
11406   { 9206 /* sw */, 2 /* 1 */, MCK_Mem, AMFBS_InMicroMips },
11422   { 9224 /* swc3 */, 2 /* 1 */, MCK_Mem, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotCnMips_NotInMicroMips },
11428   { 9233 /* swl */, 2 /* 1 */, MCK_Mem, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips },
11430   { 9233 /* swl */, 2 /* 1 */, MCK_Mem, AMFBS_InMicroMips_NotMips32r6 },
11435   { 9242 /* swm */, 2 /* 1 */, MCK_Mem, AMFBS_InMicroMips },
11441   { 9252 /* swm32 */, 2 /* 1 */, MCK_Mem, AMFBS_InMicroMips },
11446   { 9262 /* swr */, 2 /* 1 */, MCK_Mem, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips },
11448   { 9262 /* swr */, 2 /* 1 */, MCK_Mem, AMFBS_InMicroMips_NotMips32r6 },
11524   { 9509 /* ulh */, 2 /* 1 */, MCK_Mem, AMFBS_None },
11526   { 9513 /* ulhu */, 2 /* 1 */, MCK_Mem, AMFBS_None },
11528   { 9518 /* ulw */, 2 /* 1 */, MCK_Mem, AMFBS_None },
11530   { 9522 /* ush */, 2 /* 1 */, MCK_Mem, AMFBS_None },
11532   { 9526 /* usw */, 2 /* 1 */, MCK_Mem, AMFBS_None },
11660   case MCK_Mem: