|
|
reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
|
References
gen/lib/Target/Mips/MipsGenAsmMatcher.inc 3604 case MCK_Imm: {
4696 case MCK_Imm: return "MCK_Imm";
5466 { 104 /* addiupc */, Mips::ADDIUPC_MM, Convert__GPRMM16AsmReg1_0__Imm1_1, AMFBS_InMicroMips_NotMips32r6, { MCK_GPRMM16AsmReg, MCK_Imm }, },
5468 { 122 /* addiur2 */, Mips::ADDIUR2_MM, Convert__GPRMM16AsmReg1_0__GPRMM16AsmReg1_1__Imm1_2, AMFBS_InMicroMips, { MCK_GPRMM16AsmReg, MCK_GPRMM16AsmReg, MCK_Imm }, },
5470 { 138 /* addiusp */, Mips::ADDIUSP_MM, Convert__Imm1_0, AMFBS_InMicroMips, { MCK_Imm }, },
5545 { 472 /* and */, Mips::ANDi64, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__Imm1_1, AMFBS_HasStdEnc_IsGP64bit_HasMips3_NotInMicroMips, { MCK_GPR64AsmReg, MCK_Imm }, },
5552 { 472 /* and */, Mips::ANDi64, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__Imm1_2, AMFBS_HasStdEnc_IsGP64bit_HasMips3_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_Imm }, },
5563 { 500 /* andi16 */, Mips::ANDI16_MM, Convert__GPRMM16AsmReg1_0__GPRMM16AsmReg1_1__Imm1_2, AMFBS_InMicroMips_NotMips32r6, { MCK_GPRMM16AsmReg, MCK_GPRMM16AsmReg, MCK_Imm }, },
5564 { 500 /* andi16 */, Mips::ANDI16_MMR6, Convert__GPRMM16AsmReg1_0__GPRMM16AsmReg1_1__Imm1_2, AMFBS_InMicroMips_HasMips32r6, { MCK_GPRMM16AsmReg, MCK_GPRMM16AsmReg, MCK_Imm }, },
5650 { 938 /* beq */, Mips::BeqImm, Convert__GPR32AsmReg1_0__Imm1_1__JumpTarget1_2, AMFBS_None, { MCK_GPR32AsmReg, MCK_Imm, MCK_JumpTarget }, },
5655 { 947 /* beql */, Mips::BEQLImmMacro, Convert__GPR32AsmReg1_0__Imm1_1__JumpTarget1_2, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6, { MCK_GPR32AsmReg, MCK_Imm, MCK_JumpTarget }, },
5671 { 992 /* bge */, Mips::BGEImmMacro, Convert__GPR32AsmReg1_0__Imm1_1__JumpTarget1_2, AMFBS_None, { MCK_GPR32AsmReg, MCK_Imm, MCK_JumpTarget }, },
5676 { 1001 /* bgel */, Mips::BGELImmMacro, Convert__GPR32AsmReg1_0__Imm1_1__JumpTarget1_2, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6, { MCK_GPR32AsmReg, MCK_Imm, MCK_JumpTarget }, },
5678 { 1006 /* bgeu */, Mips::BGEUImmMacro, Convert__GPR32AsmReg1_0__Imm1_1__JumpTarget1_2, AMFBS_None, { MCK_GPR32AsmReg, MCK_Imm, MCK_JumpTarget }, },
5683 { 1017 /* bgeul */, Mips::BGEULImmMacro, Convert__GPR32AsmReg1_0__Imm1_1__JumpTarget1_2, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6, { MCK_GPR32AsmReg, MCK_Imm, MCK_JumpTarget }, },
5697 { 1071 /* bgt */, Mips::BGTImmMacro, Convert__GPR32AsmReg1_0__Imm1_1__JumpTarget1_2, AMFBS_None, { MCK_GPR32AsmReg, MCK_Imm, MCK_JumpTarget }, },
5699 { 1075 /* bgtl */, Mips::BGTLImmMacro, Convert__GPR32AsmReg1_0__Imm1_1__JumpTarget1_2, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6, { MCK_GPR32AsmReg, MCK_Imm, MCK_JumpTarget }, },
5701 { 1080 /* bgtu */, Mips::BGTUImmMacro, Convert__GPR32AsmReg1_0__Imm1_1__JumpTarget1_2, AMFBS_None, { MCK_GPR32AsmReg, MCK_Imm, MCK_JumpTarget }, },
5703 { 1085 /* bgtul */, Mips::BGTULImmMacro, Convert__GPR32AsmReg1_0__Imm1_1__JumpTarget1_2, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6, { MCK_GPR32AsmReg, MCK_Imm, MCK_JumpTarget }, },
5733 { 1267 /* ble */, Mips::BLEImmMacro, Convert__GPR32AsmReg1_0__Imm1_1__JumpTarget1_2, AMFBS_None, { MCK_GPR32AsmReg, MCK_Imm, MCK_JumpTarget }, },
5735 { 1271 /* blel */, Mips::BLELImmMacro, Convert__GPR32AsmReg1_0__Imm1_1__JumpTarget1_2, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6, { MCK_GPR32AsmReg, MCK_Imm, MCK_JumpTarget }, },
5737 { 1276 /* bleu */, Mips::BLEUImmMacro, Convert__GPR32AsmReg1_0__Imm1_1__JumpTarget1_2, AMFBS_None, { MCK_GPR32AsmReg, MCK_Imm, MCK_JumpTarget }, },
5739 { 1281 /* bleul */, Mips::BLEULImmMacro, Convert__GPR32AsmReg1_0__Imm1_1__JumpTarget1_2, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6, { MCK_GPR32AsmReg, MCK_Imm, MCK_JumpTarget }, },
5749 { 1312 /* blt */, Mips::BLTImmMacro, Convert__GPR32AsmReg1_0__Imm1_1__JumpTarget1_2, AMFBS_None, { MCK_GPR32AsmReg, MCK_Imm, MCK_JumpTarget }, },
5754 { 1321 /* bltl */, Mips::BLTLImmMacro, Convert__GPR32AsmReg1_0__Imm1_1__JumpTarget1_2, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6, { MCK_GPR32AsmReg, MCK_Imm, MCK_JumpTarget }, },
5756 { 1326 /* bltu */, Mips::BLTUImmMacro, Convert__GPR32AsmReg1_0__Imm1_1__JumpTarget1_2, AMFBS_None, { MCK_GPR32AsmReg, MCK_Imm, MCK_JumpTarget }, },
5761 { 1337 /* bltul */, Mips::BLTULImmMacro, Convert__GPR32AsmReg1_0__Imm1_1__JumpTarget1_2, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6, { MCK_GPR32AsmReg, MCK_Imm, MCK_JumpTarget }, },
5780 { 1419 /* bne */, Mips::BneImm, Convert__GPR32AsmReg1_0__Imm1_1__JumpTarget1_2, AMFBS_None, { MCK_GPR32AsmReg, MCK_Imm, MCK_JumpTarget }, },
5793 { 1488 /* bnel */, Mips::BNELImmMacro, Convert__GPR32AsmReg1_0__Imm1_1__JumpTarget1_2, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6, { MCK_GPR32AsmReg, MCK_Imm, MCK_JumpTarget }, },
6289 { 3175 /* ddiv */, Mips::DSDivIMacro, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__Imm1_1, AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotInMicroMips, { MCK_GPR64AsmReg, MCK_Imm }, },
6293 { 3175 /* ddiv */, Mips::DSDivIMacro, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__Imm1_2, AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_Imm }, },
6295 { 3180 /* ddivu */, Mips::DUDivIMacro, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__Imm1_1, AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotInMicroMips, { MCK_GPR64AsmReg, MCK_Imm }, },
6299 { 3180 /* ddivu */, Mips::DUDivIMacro, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__Imm1_2, AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_Imm }, },
6356 { 3314 /* dla */, Mips::LoadAddrImm64, Convert__GPR64AsmReg1_0__Imm1_1, AMFBS_None, { MCK_GPR64AsmReg, MCK_Imm }, },
6358 { 3318 /* dli */, Mips::LoadImm64, Convert__GPR64AsmReg1_0__Imm1_1, AMFBS_None, { MCK_GPR64AsmReg, MCK_Imm }, },
6732 { 5298 /* j */, Mips::J_MM, Convert__Imm1_0, AMFBS_InMicroMips_NotMips32r6, { MCK_Imm }, },
6735 { 5300 /* jal */, Mips::JAL_MM, Convert__Imm1_0, AMFBS_InMicroMips_NotMips32r6, { MCK_Imm }, },
6758 { 5346 /* jals */, Mips::JALS_MM, Convert__Imm1_0, AMFBS_InMicroMips_NotMips32r6, { MCK_Imm }, },
6789 { 5419 /* la */, Mips::LoadAddrImm32, Convert__GPR32AsmReg1_0__Imm1_1, AMFBS_None, { MCK_GPR32AsmReg, MCK_Imm }, },
6843 { 5564 /* li.d */, Mips::LoadImmDoubleGPR, Convert__GPR32AsmReg1_0__Imm1_1, AMFBS_None, { MCK_GPR32AsmReg, MCK_Imm }, },
6844 { 5564 /* li.d */, Mips::LoadImmDoubleFGR_32, Convert__StrictlyAFGR64AsmReg1_0__Imm1_1, AMFBS_NotFP64bit_IsNotSoftFloat, { MCK_StrictlyAFGR64AsmReg, MCK_Imm }, },
6845 { 5564 /* li.d */, Mips::LoadImmDoubleFGR, Convert__StrictlyFGR64AsmReg1_0__Imm1_1, AMFBS_IsFP64bit_IsNotSoftFloat, { MCK_StrictlyFGR64AsmReg, MCK_Imm }, },
6846 { 5569 /* li.s */, Mips::LoadImmSingleGPR, Convert__GPR32AsmReg1_0__Imm1_1, AMFBS_None, { MCK_GPR32AsmReg, MCK_Imm }, },
6847 { 5569 /* li.s */, Mips::LoadImmSingleFGR, Convert__StrictlyFGR32AsmReg1_0__Imm1_1, AMFBS_IsNotSoftFloat, { MCK_StrictlyFGR32AsmReg, MCK_Imm }, },
6869 { 5604 /* lw */, Mips::LwRxPcTcpX16, Convert__Reg1_0__Imm1_1__imm_95_0, AMFBS_InMips16Mode, { MCK_CPU16Regs, MCK_Imm }, },
6878 { 5604 /* lw */, Mips::LwRxPcTcp16, Convert__Reg1_0__Imm1_1__imm_95_0, AMFBS_InMips16Mode, { MCK_CPU16Regs, MCK_Imm, MCK__HASH_, MCK_16, MCK_bit, MCK_inst }, },
7305 { 7195 /* nor */, Mips::NORImm64, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__Imm1_1, AMFBS_IsGP64bit, { MCK_GPR64AsmReg, MCK_Imm }, },
7310 { 7195 /* nor */, Mips::NORImm64, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__Imm1_2, AMFBS_IsGP64bit, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_Imm }, },
7329 { 7222 /* or */, Mips::ORi64, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__Imm1_1, AMFBS_HasStdEnc_IsGP64bit_HasMips3_NotInMicroMips, { MCK_GPR64AsmReg, MCK_Imm }, },
7336 { 7222 /* or */, Mips::ORi64, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__Imm1_2, AMFBS_HasStdEnc_IsGP64bit_HasMips3_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_Imm }, },
7577 { 8056 /* sge */, Mips::SGEImm64, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__Imm1_1, AMFBS_IsGP64bit, { MCK_GPR64AsmReg, MCK_Imm }, },
7580 { 8056 /* sge */, Mips::SGEImm64, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__Imm1_2, AMFBS_IsGP64bit, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_Imm }, },
7583 { 8060 /* sgeu */, Mips::SGEUImm64, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__Imm1_1, AMFBS_IsGP64bit, { MCK_GPR64AsmReg, MCK_Imm }, },
7586 { 8060 /* sgeu */, Mips::SGEUImm64, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__Imm1_2, AMFBS_IsGP64bit, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_Imm }, },
7590 { 8065 /* sgt */, Mips::SGTImm64, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__Imm1_1, AMFBS_IsGP64bit, { MCK_GPR64AsmReg, MCK_Imm }, },
7594 { 8065 /* sgt */, Mips::SGTImm64, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__Imm1_2, AMFBS_IsGP64bit, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_Imm }, },
7598 { 8069 /* sgtu */, Mips::SGTUImm64, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__Imm1_1, AMFBS_IsGP64bit, { MCK_GPR64AsmReg, MCK_Imm }, },
7602 { 8069 /* sgtu */, Mips::SGTUImm64, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__Imm1_2, AMFBS_IsGP64bit, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_Imm }, },
7690 { 8407 /* sll16 */, Mips::SLL16_MM, Convert__GPRMM16AsmReg1_0__GPRMM16AsmReg1_1__Imm1_2, AMFBS_InMicroMips_NotMips32r6, { MCK_GPRMM16AsmReg, MCK_GPRMM16AsmReg, MCK_Imm }, },
7691 { 8407 /* sll16 */, Mips::SLL16_MMR6, Convert__GPRMM16AsmReg1_0__GPRMM16AsmReg1_1__Imm1_2, AMFBS_InMicroMips_HasMips32r6, { MCK_GPRMM16AsmReg, MCK_GPRMM16AsmReg, MCK_Imm }, },
7702 { 8446 /* slt */, Mips::SLTImm64, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__Imm1_1, AMFBS_IsGP64bit, { MCK_GPR64AsmReg, MCK_Imm }, },
7707 { 8446 /* slt */, Mips::SLTImm64, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__Imm1_2, AMFBS_IsGP64bit, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_Imm }, },
7719 { 8461 /* sltu */, Mips::SLTUImm64, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__Imm1_1, AMFBS_IsGP64bit, { MCK_GPR64AsmReg, MCK_Imm }, },
7724 { 8461 /* sltu */, Mips::SLTUImm64, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__Imm1_2, AMFBS_IsGP64bit, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_Imm }, },
7786 { 8706 /* srl16 */, Mips::SRL16_MM, Convert__GPRMM16AsmReg1_0__GPRMM16AsmReg1_1__Imm1_2, AMFBS_InMicroMips_NotMips32r6, { MCK_GPRMM16AsmReg, MCK_GPRMM16AsmReg, MCK_Imm }, },
7787 { 8706 /* srl16 */, Mips::SRL16_MMR6, Convert__GPRMM16AsmReg1_0__GPRMM16AsmReg1_1__Imm1_2, AMFBS_InMicroMips_HasMips32r6, { MCK_GPRMM16AsmReg, MCK_GPRMM16AsmReg, MCK_Imm }, },
8049 { 9599 /* xor */, Mips::XORi64, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__Imm1_1, AMFBS_HasStdEnc_IsGP64bit_HasMips3_NotInMicroMips, { MCK_GPR64AsmReg, MCK_Imm }, },
8056 { 9599 /* xor */, Mips::XORi64, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__Imm1_2, AMFBS_HasStdEnc_IsGP64bit_HasMips3_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_Imm }, },