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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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References
gen/lib/Target/Mips/MipsGenAsmMatcher.inc 3485 case MCK_COP0AsmReg: {
4679 case MCK_COP0AsmReg: return "MCK_COP0AsmReg";
6361 { 3327 /* dmfc0 */, Mips::DMFC0, Convert__GPR64AsmReg1_0__COP0AsmReg1_1__imm_95_0, AMFBS_NotInMicroMips, { MCK_GPR64AsmReg, MCK_COP0AsmReg }, },
6362 { 3327 /* dmfc0 */, Mips::DMFC0, Convert__GPR64AsmReg1_0__COP0AsmReg1_1__ConstantUImm3_01_2, AMFBS_HasStdEnc_IsGP64bit_HasMips3, { MCK_GPR64AsmReg, MCK_COP0AsmReg, MCK_ConstantUImm3_0 }, },
6367 { 3345 /* dmfgc0 */, Mips::DMFGC0, Convert__GPR64AsmReg1_0__COP0AsmReg1_1__imm_95_0, AMFBS_HasStdEnc_HasMips64r5_HasVirt_NotInMicroMips, { MCK_GPR64AsmReg, MCK_COP0AsmReg }, },
6368 { 3345 /* dmfgc0 */, Mips::DMFGC0, Convert__GPR64AsmReg1_0__COP0AsmReg1_1__ConstantUImm3_01_2, AMFBS_HasStdEnc_HasMips64r5_HasVirt, { MCK_GPR64AsmReg, MCK_COP0AsmReg, MCK_ConstantUImm3_0 }, },
6373 { 3367 /* dmtc0 */, Mips::DMTC0, Convert__COP0AsmReg1_1__GPR64AsmReg1_0__imm_95_0, AMFBS_NotInMicroMips, { MCK_GPR64AsmReg, MCK_COP0AsmReg }, },
6374 { 3367 /* dmtc0 */, Mips::DMTC0, Convert__COP0AsmReg1_1__GPR64AsmReg1_0__ConstantUImm3_01_2, AMFBS_HasStdEnc_IsGP64bit_HasMips3, { MCK_GPR64AsmReg, MCK_COP0AsmReg, MCK_ConstantUImm3_0 }, },
6379 { 3385 /* dmtgc0 */, Mips::DMTGC0, Convert__COP0AsmReg1_1__GPR64AsmReg1_0__imm_95_0, AMFBS_HasStdEnc_HasMips64r5_HasVirt_NotInMicroMips, { MCK_GPR64AsmReg, MCK_COP0AsmReg }, },
6380 { 3385 /* dmtgc0 */, Mips::DMTGC0, Convert__COP0AsmReg1_1__GPR64AsmReg1_0__ConstantUImm3_01_2, AMFBS_HasStdEnc_HasMips64r5_HasVirt, { MCK_GPR64AsmReg, MCK_COP0AsmReg, MCK_ConstantUImm3_0 }, },
6972 { 6054 /* mfc0 */, Mips::MFC0, Convert__GPR32AsmReg1_0__COP0AsmReg1_1__imm_95_0, AMFBS_HasStdEnc_NotInMicroMips, { MCK_GPR32AsmReg, MCK_COP0AsmReg }, },
6973 { 6054 /* mfc0 */, Mips::MFC0_MMR6, Convert__GPR32AsmReg1_0__COP0AsmReg1_1__imm_95_0, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_COP0AsmReg }, },
6974 { 6054 /* mfc0 */, Mips::MFC0, Convert__GPR32AsmReg1_0__COP0AsmReg1_1__ConstantUImm3_01_2, AMFBS_HasStdEnc_NotInMicroMips, { MCK_GPR32AsmReg, MCK_COP0AsmReg, MCK_ConstantUImm3_0 }, },
6975 { 6054 /* mfc0 */, Mips::MFC0_MMR6, Convert__GPR32AsmReg1_0__COP0AsmReg1_1__ConstantUImm3_01_2, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_COP0AsmReg, MCK_ConstantUImm3_0 }, },
6983 { 6069 /* mfgc0 */, Mips::MFGC0, Convert__GPR32AsmReg1_0__COP0AsmReg1_1__imm_95_0, AMFBS_HasStdEnc_HasMips32r5_HasVirt_NotInMicroMips, { MCK_GPR32AsmReg, MCK_COP0AsmReg }, },
6984 { 6069 /* mfgc0 */, Mips::MFGC0_MM, Convert__GPR32AsmReg1_0__COP0AsmReg1_1__imm_95_0, AMFBS_InMicroMips_HasMips32r5_HasVirt, { MCK_GPR32AsmReg, MCK_COP0AsmReg }, },
6985 { 6069 /* mfgc0 */, Mips::MFGC0, Convert__GPR32AsmReg1_0__COP0AsmReg1_1__ConstantUImm3_01_2, AMFBS_HasStdEnc_HasMips32r5_HasVirt_NotInMicroMips, { MCK_GPR32AsmReg, MCK_COP0AsmReg, MCK_ConstantUImm3_0 }, },
6986 { 6069 /* mfgc0 */, Mips::MFGC0_MM, Convert__GPR32AsmReg1_0__COP0AsmReg1_1__ConstantUImm3_01_2, AMFBS_InMicroMips_HasMips32r5_HasVirt, { MCK_GPR32AsmReg, MCK_COP0AsmReg, MCK_ConstantUImm3_0 }, },
6987 { 6075 /* mfhc0 */, Mips::MFHC0_MMR6, Convert__GPR32AsmReg1_0__COP0AsmReg1_1__imm_95_0, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_COP0AsmReg }, },
6988 { 6075 /* mfhc0 */, Mips::MFHC0_MMR6, Convert__GPR32AsmReg1_0__COP0AsmReg1_1__ConstantUImm3_01_2, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_COP0AsmReg, MCK_ConstantUImm3_0 }, },
6994 { 6093 /* mfhgc0 */, Mips::MFHGC0, Convert__GPR32AsmReg1_0__COP0AsmReg1_1__imm_95_0, AMFBS_HasStdEnc_HasMips32r5_HasVirt_NotInMicroMips, { MCK_GPR32AsmReg, MCK_COP0AsmReg }, },
6995 { 6093 /* mfhgc0 */, Mips::MFHGC0_MM, Convert__GPR32AsmReg1_0__COP0AsmReg1_1__imm_95_0, AMFBS_InMicroMips_HasMips32r5_HasVirt, { MCK_GPR32AsmReg, MCK_COP0AsmReg }, },
6996 { 6093 /* mfhgc0 */, Mips::MFHGC0, Convert__GPR32AsmReg1_0__COP0AsmReg1_1__ConstantUImm3_01_2, AMFBS_HasStdEnc_HasMips32r5_HasVirt_NotInMicroMips, { MCK_GPR32AsmReg, MCK_COP0AsmReg, MCK_ConstantUImm3_0 }, },
6997 { 6093 /* mfhgc0 */, Mips::MFHGC0_MM, Convert__GPR32AsmReg1_0__COP0AsmReg1_1__ConstantUImm3_01_2, AMFBS_InMicroMips_HasMips32r5_HasVirt, { MCK_GPR32AsmReg, MCK_COP0AsmReg, MCK_ConstantUImm3_0 }, },
7012 { 6131 /* mftc0 */, Mips::MFTC0, Convert__GPR32AsmReg1_0__COP0AsmReg1_1__imm_95_0, AMFBS_HasMT_NotInMicroMips, { MCK_GPR32AsmReg, MCK_COP0AsmReg }, },
7013 { 6131 /* mftc0 */, Mips::MFTC0, Convert__GPR32AsmReg1_0__COP0AsmReg1_1__ConstantUImm3_01_2, AMFBS_HasMT, { MCK_GPR32AsmReg, MCK_COP0AsmReg, MCK_ConstantUImm3_0 }, },
7137 { 6679 /* mtc0 */, Mips::MTC0, Convert__COP0AsmReg1_1__GPR32AsmReg1_0__imm_95_0, AMFBS_HasStdEnc_NotInMicroMips, { MCK_GPR32AsmReg, MCK_COP0AsmReg }, },
7138 { 6679 /* mtc0 */, Mips::MTC0_MMR6, Convert__COP0AsmReg1_1__GPR32AsmReg1_0__imm_95_0, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_COP0AsmReg }, },
7139 { 6679 /* mtc0 */, Mips::MTC0, Convert__COP0AsmReg1_1__GPR32AsmReg1_0__ConstantUImm3_01_2, AMFBS_HasStdEnc_NotInMicroMips, { MCK_GPR32AsmReg, MCK_COP0AsmReg, MCK_ConstantUImm3_0 }, },
7140 { 6679 /* mtc0 */, Mips::MTC0_MMR6, Convert__COP0AsmReg1_1__GPR32AsmReg1_0__ConstantUImm3_01_2, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_COP0AsmReg, MCK_ConstantUImm3_0 }, },
7149 { 6694 /* mtgc0 */, Mips::MTGC0, Convert__COP0AsmReg1_1__GPR32AsmReg1_0__imm_95_0, AMFBS_HasStdEnc_HasMips32r5_HasVirt_NotInMicroMips, { MCK_GPR32AsmReg, MCK_COP0AsmReg }, },
7150 { 6694 /* mtgc0 */, Mips::MTGC0_MM, Convert__COP0AsmReg1_1__GPR32AsmReg1_0__imm_95_0, AMFBS_InMicroMips_HasMips32r5_HasVirt, { MCK_GPR32AsmReg, MCK_COP0AsmReg }, },
7151 { 6694 /* mtgc0 */, Mips::MTGC0, Convert__COP0AsmReg1_1__GPR32AsmReg1_0__ConstantUImm3_01_2, AMFBS_HasStdEnc_HasMips32r5_HasVirt_NotInMicroMips, { MCK_GPR32AsmReg, MCK_COP0AsmReg, MCK_ConstantUImm3_0 }, },
7152 { 6694 /* mtgc0 */, Mips::MTGC0_MM, Convert__COP0AsmReg1_1__GPR32AsmReg1_0__ConstantUImm3_01_2, AMFBS_InMicroMips_HasMips32r5_HasVirt, { MCK_GPR32AsmReg, MCK_COP0AsmReg, MCK_ConstantUImm3_0 }, },
7153 { 6700 /* mthc0 */, Mips::MTHC0_MMR6, Convert__COP0AsmReg1_1__GPR32AsmReg1_0__imm_95_0, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_COP0AsmReg }, },
7154 { 6700 /* mthc0 */, Mips::MTHC0_MMR6, Convert__COP0AsmReg1_1__GPR32AsmReg1_0__ConstantUImm3_01_2, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_COP0AsmReg, MCK_ConstantUImm3_0 }, },
7160 { 6718 /* mthgc0 */, Mips::MTHGC0, Convert__COP0AsmReg1_1__GPR32AsmReg1_0__imm_95_0, AMFBS_HasStdEnc_HasMips32r5_HasVirt_NotInMicroMips, { MCK_GPR32AsmReg, MCK_COP0AsmReg }, },
7161 { 6718 /* mthgc0 */, Mips::MTHGC0_MM, Convert__COP0AsmReg1_1__GPR32AsmReg1_0__imm_95_0, AMFBS_InMicroMips_HasMips32r5_HasVirt, { MCK_GPR32AsmReg, MCK_COP0AsmReg }, },
7162 { 6718 /* mthgc0 */, Mips::MTHGC0, Convert__COP0AsmReg1_1__GPR32AsmReg1_0__ConstantUImm3_01_2, AMFBS_HasStdEnc_HasMips32r5_HasVirt_NotInMicroMips, { MCK_GPR32AsmReg, MCK_COP0AsmReg, MCK_ConstantUImm3_0 }, },
7163 { 6718 /* mthgc0 */, Mips::MTHGC0_MM, Convert__COP0AsmReg1_1__GPR32AsmReg1_0__ConstantUImm3_01_2, AMFBS_InMicroMips_HasMips32r5_HasVirt, { MCK_GPR32AsmReg, MCK_COP0AsmReg, MCK_ConstantUImm3_0 }, },
7182 { 6779 /* mttc0 */, Mips::MTTC0, Convert__COP0AsmReg1_1__GPR32AsmReg1_0__imm_95_0, AMFBS_HasMT_NotInMicroMips, { MCK_GPR32AsmReg, MCK_COP0AsmReg }, },
7183 { 6779 /* mttc0 */, Mips::MTTC0, Convert__COP0AsmReg1_1__GPR32AsmReg1_0__ConstantUImm3_01_2, AMFBS_HasMT, { MCK_GPR32AsmReg, MCK_COP0AsmReg, MCK_ConstantUImm3_0 }, },
9551 { 3327 /* dmfc0 */, 2 /* 1 */, MCK_COP0AsmReg, AMFBS_NotInMicroMips },
9553 { 3327 /* dmfc0 */, 2 /* 1 */, MCK_COP0AsmReg, AMFBS_HasStdEnc_IsGP64bit_HasMips3 },
9562 { 3345 /* dmfgc0 */, 2 /* 1 */, MCK_COP0AsmReg, AMFBS_HasStdEnc_HasMips64r5_HasVirt_NotInMicroMips },
9564 { 3345 /* dmfgc0 */, 2 /* 1 */, MCK_COP0AsmReg, AMFBS_HasStdEnc_HasMips64r5_HasVirt },
9569 { 3367 /* dmtc0 */, 2 /* 1 */, MCK_COP0AsmReg, AMFBS_NotInMicroMips },
9571 { 3367 /* dmtc0 */, 2 /* 1 */, MCK_COP0AsmReg, AMFBS_HasStdEnc_IsGP64bit_HasMips3 },
9580 { 3385 /* dmtgc0 */, 2 /* 1 */, MCK_COP0AsmReg, AMFBS_HasStdEnc_HasMips64r5_HasVirt_NotInMicroMips },
9582 { 3385 /* dmtgc0 */, 2 /* 1 */, MCK_COP0AsmReg, AMFBS_HasStdEnc_HasMips64r5_HasVirt },
10331 { 6054 /* mfc0 */, 2 /* 1 */, MCK_COP0AsmReg, AMFBS_HasStdEnc_NotInMicroMips },
10333 { 6054 /* mfc0 */, 2 /* 1 */, MCK_COP0AsmReg, AMFBS_InMicroMips_HasMips32r6 },
10335 { 6054 /* mfc0 */, 2 /* 1 */, MCK_COP0AsmReg, AMFBS_HasStdEnc_NotInMicroMips },
10337 { 6054 /* mfc0 */, 2 /* 1 */, MCK_COP0AsmReg, AMFBS_InMicroMips_HasMips32r6 },
10353 { 6069 /* mfgc0 */, 2 /* 1 */, MCK_COP0AsmReg, AMFBS_HasStdEnc_HasMips32r5_HasVirt_NotInMicroMips },
10355 { 6069 /* mfgc0 */, 2 /* 1 */, MCK_COP0AsmReg, AMFBS_InMicroMips_HasMips32r5_HasVirt },
10357 { 6069 /* mfgc0 */, 2 /* 1 */, MCK_COP0AsmReg, AMFBS_HasStdEnc_HasMips32r5_HasVirt_NotInMicroMips },
10359 { 6069 /* mfgc0 */, 2 /* 1 */, MCK_COP0AsmReg, AMFBS_InMicroMips_HasMips32r5_HasVirt },
10361 { 6075 /* mfhc0 */, 2 /* 1 */, MCK_COP0AsmReg, AMFBS_InMicroMips_HasMips32r6 },
10363 { 6075 /* mfhc0 */, 2 /* 1 */, MCK_COP0AsmReg, AMFBS_InMicroMips_HasMips32r6 },
10375 { 6093 /* mfhgc0 */, 2 /* 1 */, MCK_COP0AsmReg, AMFBS_HasStdEnc_HasMips32r5_HasVirt_NotInMicroMips },
10377 { 6093 /* mfhgc0 */, 2 /* 1 */, MCK_COP0AsmReg, AMFBS_InMicroMips_HasMips32r5_HasVirt },
10379 { 6093 /* mfhgc0 */, 2 /* 1 */, MCK_COP0AsmReg, AMFBS_HasStdEnc_HasMips32r5_HasVirt_NotInMicroMips },
10381 { 6093 /* mfhgc0 */, 2 /* 1 */, MCK_COP0AsmReg, AMFBS_InMicroMips_HasMips32r5_HasVirt },
10400 { 6131 /* mftc0 */, 2 /* 1 */, MCK_COP0AsmReg, AMFBS_HasMT_NotInMicroMips },
10402 { 6131 /* mftc0 */, 2 /* 1 */, MCK_COP0AsmReg, AMFBS_HasMT },
10561 { 6679 /* mtc0 */, 2 /* 1 */, MCK_COP0AsmReg, AMFBS_HasStdEnc_NotInMicroMips },
10563 { 6679 /* mtc0 */, 2 /* 1 */, MCK_COP0AsmReg, AMFBS_InMicroMips_HasMips32r6 },
10565 { 6679 /* mtc0 */, 2 /* 1 */, MCK_COP0AsmReg, AMFBS_HasStdEnc_NotInMicroMips },
10567 { 6679 /* mtc0 */, 2 /* 1 */, MCK_COP0AsmReg, AMFBS_InMicroMips_HasMips32r6 },
10585 { 6694 /* mtgc0 */, 2 /* 1 */, MCK_COP0AsmReg, AMFBS_HasStdEnc_HasMips32r5_HasVirt_NotInMicroMips },
10587 { 6694 /* mtgc0 */, 2 /* 1 */, MCK_COP0AsmReg, AMFBS_InMicroMips_HasMips32r5_HasVirt },
10589 { 6694 /* mtgc0 */, 2 /* 1 */, MCK_COP0AsmReg, AMFBS_HasStdEnc_HasMips32r5_HasVirt_NotInMicroMips },
10591 { 6694 /* mtgc0 */, 2 /* 1 */, MCK_COP0AsmReg, AMFBS_InMicroMips_HasMips32r5_HasVirt },
10593 { 6700 /* mthc0 */, 2 /* 1 */, MCK_COP0AsmReg, AMFBS_InMicroMips_HasMips32r6 },
10595 { 6700 /* mthc0 */, 2 /* 1 */, MCK_COP0AsmReg, AMFBS_InMicroMips_HasMips32r6 },
10607 { 6718 /* mthgc0 */, 2 /* 1 */, MCK_COP0AsmReg, AMFBS_HasStdEnc_HasMips32r5_HasVirt_NotInMicroMips },
10609 { 6718 /* mthgc0 */, 2 /* 1 */, MCK_COP0AsmReg, AMFBS_InMicroMips_HasMips32r5_HasVirt },
10611 { 6718 /* mthgc0 */, 2 /* 1 */, MCK_COP0AsmReg, AMFBS_HasStdEnc_HasMips32r5_HasVirt_NotInMicroMips },
10613 { 6718 /* mthgc0 */, 2 /* 1 */, MCK_COP0AsmReg, AMFBS_InMicroMips_HasMips32r5_HasVirt },
10640 { 6779 /* mttc0 */, 2 /* 1 */, MCK_COP0AsmReg, AMFBS_HasMT_NotInMicroMips },
10642 { 6779 /* mttc0 */, 2 /* 1 */, MCK_COP0AsmReg, AMFBS_HasMT },
11590 case MCK_COP0AsmReg: