reference, declaration → definition definition → references, declarations, derived classes, virtual overrides reference to multiple definitions → definitions unreferenced |
5435 { 45 /* add */, Mips::ADDi, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm32_Relaxed1_2, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_SImm32_Relaxed }, }, 5436 { 45 /* add */, Mips::ADDi_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm32_Relaxed1_2, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_SImm32_Relaxed }, }, 5508 { 325 /* addu */, Mips::ADDiu, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm32_Relaxed1_2, AMFBS_HasStdEnc_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_SImm32_Relaxed }, }, 5509 { 325 /* addu */, Mips::ADDiu_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm32_Relaxed1_2, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_SImm32_Relaxed }, }, 5550 { 472 /* and */, Mips::ANDi, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm32_Relaxed1_2, AMFBS_HasStdEnc_IsGP32bit_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_SImm32_Relaxed }, }, 5551 { 472 /* and */, Mips::ANDi_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm32_Relaxed1_2, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_SImm32_Relaxed }, }, 7206 { 6838 /* mul */, Mips::MULImmMacro, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm32_Relaxed1_2, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_SImm32_Relaxed }, }, 7309 { 7195 /* nor */, Mips::NORImm, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm32_Relaxed1_2, AMFBS_IsGP32bit, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_SImm32_Relaxed }, }, 7334 { 7222 /* or */, Mips::ORi, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm32_Relaxed1_2, AMFBS_HasStdEnc_IsGP32bit_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_SImm32_Relaxed }, }, 7335 { 7222 /* or */, Mips::ORi_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm32_Relaxed1_2, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_SImm32_Relaxed }, }, 7436 { 7704 /* rem */, Mips::SRemIMacro, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm32_Relaxed1_2, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_SImm32_Relaxed }, }, 7440 { 7708 /* remu */, Mips::URemIMacro, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm32_Relaxed1_2, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_SImm32_Relaxed }, }, 7571 { 8047 /* seq */, Mips::SEQIMacro, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm32_Relaxed1_2, AMFBS_NotCnMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_SImm32_Relaxed }, }, 7705 { 8446 /* slt */, Mips::SLTi, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm32_Relaxed1_2, AMFBS_HasStdEnc_IsGP32bit_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_SImm32_Relaxed }, }, 7706 { 8446 /* slt */, Mips::SLTi_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm32_Relaxed1_2, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_SImm32_Relaxed }, }, 7722 { 8461 /* sltu */, Mips::SLTiu, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm32_Relaxed1_2, AMFBS_HasStdEnc_IsGP32bit_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_SImm32_Relaxed }, }, 7723 { 8461 /* sltu */, Mips::SLTiu_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm32_Relaxed1_2, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_SImm32_Relaxed }, }, 8054 { 9599 /* xor */, Mips::XORi, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm32_Relaxed1_2, AMFBS_HasStdEnc_IsGP32bit_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_SImm32_Relaxed }, }, 8055 { 9599 /* xor */, Mips::XORi_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm32_Relaxed1_2, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_SImm32_Relaxed }, },