reference, declaration → definition definition → references, declarations, derived classes, virtual overrides reference to multiple definitions → definitions unreferenced |
5417 { 4 /* abs.d */, Mips::FABS_D64, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1, AMFBS_HasStdEnc_IsFP64bit_IsNotSoftFloat_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, 5418 { 4 /* abs.d */, Mips::FABS_D64_MM, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1, AMFBS_InMicroMips_IsFP64bit_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, 6047 { 1975 /* ceil.l.d */, Mips::CEIL_L_D64, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1, AMFBS_HasStdEnc_IsFP64bit_HasMips3_32_IsNotSoftFloat_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, 6048 { 1975 /* ceil.l.d */, Mips::CEIL_L_D_MMR6, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, 6077 { 2098 /* class.d */, Mips::CLASS_D, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, 6078 { 2098 /* class.d */, Mips::CLASS_D_MMR6, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1, AMFBS_InMicroMips_HasMips32r6, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, 6232 { 3003 /* cvt.d.l */, Mips::CVT_D64_L, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1, AMFBS_HasStdEnc_IsFP64bit_HasMips3_32r2_IsNotSoftFloat_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, 6233 { 3003 /* cvt.d.l */, Mips::CVT_D_L_MMR6, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1, AMFBS_InMicroMips_IsFP64bit_HasMips32r6_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, 6242 { 3027 /* cvt.l.d */, Mips::CVT_L_D64, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1, AMFBS_HasStdEnc_HasMips3_32r2_IsNotSoftFloat_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, 6243 { 3027 /* cvt.l.d */, Mips::CVT_L_D64_MM, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1, AMFBS_InMicroMips_IsFP64bit_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, 6244 { 3027 /* cvt.l.d */, Mips::CVT_L_D_MMR6, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, 6613 { 4482 /* floor.l.d */, Mips::FLOOR_L_D64, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1, AMFBS_HasStdEnc_IsFP64bit_HasMips3_32_IsNotSoftFloat_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, 6614 { 4482 /* floor.l.d */, Mips::FLOOR_L_D_MMR6, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, 7067 { 6455 /* mov.d */, Mips::FMOV_D64, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1, AMFBS_HasStdEnc_IsFP64bit_IsNotSoftFloat_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, 7068 { 6455 /* mov.d */, Mips::FMOV_D64_MM, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1, AMFBS_InMicroMips_IsFP64bit_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, 7069 { 6455 /* mov.d */, Mips::FMOV_D_MMR6, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, 7270 { 7086 /* neg.d */, Mips::FNEG_D64, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1, AMFBS_HasStdEnc_IsFP64bit_IsNotSoftFloat_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, 7271 { 7086 /* neg.d */, Mips::FNEG_D64_MM, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1, AMFBS_InMicroMips_IsFP64bit_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, 7429 { 7688 /* recip.d */, Mips::RECIP_D64, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1, AMFBS_HasStdEnc_IsFP64bit_HasMips4_32r2_IsNotSoftFloat_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, 7430 { 7688 /* recip.d */, Mips::RECIP_D64_MM, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1, AMFBS_InMicroMips_IsFP64bit_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, 7449 { 7747 /* rint.d */, Mips::RINT_D, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, 7450 { 7747 /* rint.d */, Mips::RINT_D_MMR6, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1, AMFBS_InMicroMips_HasMips32r6, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, 7468 { 7780 /* round.l.d */, Mips::ROUND_L_D64, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1, AMFBS_HasStdEnc_IsFP64bit_HasMips3_32_IsNotSoftFloat_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, 7469 { 7780 /* round.l.d */, Mips::ROUND_L_D_MMR6, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, 7475 { 7800 /* round.w.d */, Mips::ROUND_W_D_MMR6, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, 7481 { 7820 /* rsqrt.d */, Mips::RSQRT_D64, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1, AMFBS_HasStdEnc_IsFP64bit_HasMips4_32r2_IsNotSoftFloat_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, 7482 { 7820 /* rsqrt.d */, Mips::RSQRT_D64_MM, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1, AMFBS_InMicroMips_IsFP64bit_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, 7739 { 8543 /* sqrt.d */, Mips::FSQRT_D64, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1, AMFBS_HasStdEnc_IsFP64bit_HasMips2_IsNotSoftFloat_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, 7740 { 8543 /* sqrt.d */, Mips::FSQRT_D64_MM, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1, AMFBS_InMicroMips_IsFP64bit_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, 8001 { 9469 /* trunc.l.d */, Mips::TRUNC_L_D64, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1, AMFBS_HasStdEnc_IsFP64bit_HasMips3_32_IsNotSoftFloat_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, 8002 { 9469 /* trunc.l.d */, Mips::TRUNC_L_D_MMR6, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },