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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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References
gen/lib/Target/Mips/MipsGenAsmMatcher.inc 5414 { 0 /* abs */, Mips::ABSMacro, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_None, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
5598 { 732 /* b */, Mips::B_MMR6_Pseudo, Convert__JumpTarget1_0, AMFBS_None, { MCK_JumpTarget }, },
5650 { 938 /* beq */, Mips::BeqImm, Convert__GPR32AsmReg1_0__Imm1_1__JumpTarget1_2, AMFBS_None, { MCK_GPR32AsmReg, MCK_Imm, MCK_JumpTarget }, },
5670 { 992 /* bge */, Mips::BGE, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__JumpTarget1_2, AMFBS_None, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_JumpTarget }, },
5671 { 992 /* bge */, Mips::BGEImmMacro, Convert__GPR32AsmReg1_0__Imm1_1__JumpTarget1_2, AMFBS_None, { MCK_GPR32AsmReg, MCK_Imm, MCK_JumpTarget }, },
5677 { 1006 /* bgeu */, Mips::BGEU, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__JumpTarget1_2, AMFBS_None, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_JumpTarget }, },
5678 { 1006 /* bgeu */, Mips::BGEUImmMacro, Convert__GPR32AsmReg1_0__Imm1_1__JumpTarget1_2, AMFBS_None, { MCK_GPR32AsmReg, MCK_Imm, MCK_JumpTarget }, },
5696 { 1071 /* bgt */, Mips::BGT, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__JumpTarget1_2, AMFBS_None, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_JumpTarget }, },
5697 { 1071 /* bgt */, Mips::BGTImmMacro, Convert__GPR32AsmReg1_0__Imm1_1__JumpTarget1_2, AMFBS_None, { MCK_GPR32AsmReg, MCK_Imm, MCK_JumpTarget }, },
5700 { 1080 /* bgtu */, Mips::BGTU, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__JumpTarget1_2, AMFBS_None, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_JumpTarget }, },
5701 { 1080 /* bgtu */, Mips::BGTUImmMacro, Convert__GPR32AsmReg1_0__Imm1_1__JumpTarget1_2, AMFBS_None, { MCK_GPR32AsmReg, MCK_Imm, MCK_JumpTarget }, },
5732 { 1267 /* ble */, Mips::BLE, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__JumpTarget1_2, AMFBS_None, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_JumpTarget }, },
5733 { 1267 /* ble */, Mips::BLEImmMacro, Convert__GPR32AsmReg1_0__Imm1_1__JumpTarget1_2, AMFBS_None, { MCK_GPR32AsmReg, MCK_Imm, MCK_JumpTarget }, },
5736 { 1276 /* bleu */, Mips::BLEU, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__JumpTarget1_2, AMFBS_None, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_JumpTarget }, },
5737 { 1276 /* bleu */, Mips::BLEUImmMacro, Convert__GPR32AsmReg1_0__Imm1_1__JumpTarget1_2, AMFBS_None, { MCK_GPR32AsmReg, MCK_Imm, MCK_JumpTarget }, },
5748 { 1312 /* blt */, Mips::BLT, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__JumpTarget1_2, AMFBS_None, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_JumpTarget }, },
5749 { 1312 /* blt */, Mips::BLTImmMacro, Convert__GPR32AsmReg1_0__Imm1_1__JumpTarget1_2, AMFBS_None, { MCK_GPR32AsmReg, MCK_Imm, MCK_JumpTarget }, },
5755 { 1326 /* bltu */, Mips::BLTU, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__JumpTarget1_2, AMFBS_None, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_JumpTarget }, },
5756 { 1326 /* bltu */, Mips::BLTUImmMacro, Convert__GPR32AsmReg1_0__Imm1_1__JumpTarget1_2, AMFBS_None, { MCK_GPR32AsmReg, MCK_Imm, MCK_JumpTarget }, },
5780 { 1419 /* bne */, Mips::BneImm, Convert__GPR32AsmReg1_0__Imm1_1__JumpTarget1_2, AMFBS_None, { MCK_GPR32AsmReg, MCK_Imm, MCK_JumpTarget }, },
6356 { 3314 /* dla */, Mips::LoadAddrImm64, Convert__GPR64AsmReg1_0__Imm1_1, AMFBS_None, { MCK_GPR64AsmReg, MCK_Imm }, },
6357 { 3314 /* dla */, Mips::LoadAddrReg64, Convert__GPR64AsmReg1_0__Mem2_1, AMFBS_None, { MCK_GPR64AsmReg, MCK_Mem }, },
6358 { 3318 /* dli */, Mips::LoadImm64, Convert__GPR64AsmReg1_0__Imm1_1, AMFBS_None, { MCK_GPR64AsmReg, MCK_Imm }, },
6364 { 3339 /* dmfc2 */, Mips::DMFC2, Convert__GPR64AsmReg1_0__COP2AsmReg1_1__imm_95_0, AMFBS_None, { MCK_GPR64AsmReg, MCK_COP2AsmReg }, },
6376 { 3379 /* dmtc2 */, Mips::DMTC2, Convert__COP2AsmReg1_1__GPR64AsmReg1_0__imm_95_0, AMFBS_None, { MCK_GPR64AsmReg, MCK_COP2AsmReg }, },
6734 { 5300 /* jal */, Mips::JalOneReg, Convert__GPR32AsmReg1_0, AMFBS_None, { MCK_GPR32AsmReg }, },
6738 { 5300 /* jal */, Mips::JalTwoReg, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_None, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
6789 { 5419 /* la */, Mips::LoadAddrImm32, Convert__GPR32AsmReg1_0__Imm1_1, AMFBS_None, { MCK_GPR32AsmReg, MCK_Imm }, },
6790 { 5419 /* la */, Mips::LoadAddrReg32, Convert__GPR32AsmReg1_0__Mem2_1, AMFBS_None, { MCK_GPR32AsmReg, MCK_Mem }, },
6841 { 5561 /* li */, Mips::LoadImm32, Convert__GPR32AsmReg1_0__UImm32_Coerced1_1, AMFBS_None, { MCK_GPR32AsmReg, MCK_UImm32_Coerced }, },
6843 { 5564 /* li.d */, Mips::LoadImmDoubleGPR, Convert__GPR32AsmReg1_0__Imm1_1, AMFBS_None, { MCK_GPR32AsmReg, MCK_Imm }, },
6846 { 5569 /* li.s */, Mips::LoadImmSingleGPR, Convert__GPR32AsmReg1_0__Imm1_1, AMFBS_None, { MCK_GPR32AsmReg, MCK_Imm }, },
7453 { 7761 /* rol */, Mips::ROL, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_None, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7454 { 7761 /* rol */, Mips::ROLImm, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__SImm161_1, AMFBS_None, { MCK_GPR32AsmReg, MCK_SImm16 }, },
7455 { 7761 /* rol */, Mips::ROL, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_None, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7456 { 7761 /* rol */, Mips::ROLImm, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm161_2, AMFBS_None, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_SImm16 }, },
7457 { 7765 /* ror */, Mips::ROR, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_None, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7458 { 7765 /* ror */, Mips::RORImm, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__SImm161_1, AMFBS_None, { MCK_GPR32AsmReg, MCK_SImm16 }, },
7459 { 7765 /* ror */, Mips::ROR, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_None, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7460 { 7765 /* ror */, Mips::RORImm, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm161_2, AMFBS_None, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_SImm16 }, },
7858 { 9072 /* subu */, Mips::ADDiu, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__InvNum1_1, AMFBS_None, { MCK_GPR32AsmReg, MCK_InvNum }, },
7863 { 9072 /* subu */, Mips::ADDiu, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__InvNum1_2, AMFBS_None, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_InvNum }, },
8014 { 9499 /* trunc.w.s */, Mips::PseudoTRUNC_W_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_None, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_GPR32AsmReg }, },
8015 { 9509 /* ulh */, Mips::Ulh, Convert__GPR32AsmReg1_0__Mem2_1, AMFBS_None, { MCK_GPR32AsmReg, MCK_Mem }, },
8016 { 9513 /* ulhu */, Mips::Ulhu, Convert__GPR32AsmReg1_0__Mem2_1, AMFBS_None, { MCK_GPR32AsmReg, MCK_Mem }, },
8017 { 9518 /* ulw */, Mips::Ulw, Convert__GPR32AsmReg1_0__Mem2_1, AMFBS_None, { MCK_GPR32AsmReg, MCK_Mem }, },
8018 { 9522 /* ush */, Mips::Ush, Convert__GPR32AsmReg1_0__Mem2_1, AMFBS_None, { MCK_GPR32AsmReg, MCK_Mem }, },
8019 { 9526 /* usw */, Mips::Usw, Convert__GPR32AsmReg1_0__Mem2_1, AMFBS_None, { MCK_GPR32AsmReg, MCK_Mem }, },
8299 { 0 /* abs */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_None },
8474 { 732 /* b */, 1 /* 0 */, MCK_JumpTarget, AMFBS_None },
8548 { 938 /* beq */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_None },
8549 { 938 /* beq */, 4 /* 2 */, MCK_JumpTarget, AMFBS_None },
8586 { 992 /* bge */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_None },
8587 { 992 /* bge */, 4 /* 2 */, MCK_JumpTarget, AMFBS_None },
8588 { 992 /* bge */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_None },
8589 { 992 /* bge */, 4 /* 2 */, MCK_JumpTarget, AMFBS_None },
8600 { 1006 /* bgeu */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_None },
8601 { 1006 /* bgeu */, 4 /* 2 */, MCK_JumpTarget, AMFBS_None },
8602 { 1006 /* bgeu */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_None },
8603 { 1006 /* bgeu */, 4 /* 2 */, MCK_JumpTarget, AMFBS_None },
8638 { 1071 /* bgt */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_None },
8639 { 1071 /* bgt */, 4 /* 2 */, MCK_JumpTarget, AMFBS_None },
8640 { 1071 /* bgt */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_None },
8641 { 1071 /* bgt */, 4 /* 2 */, MCK_JumpTarget, AMFBS_None },
8646 { 1080 /* bgtu */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_None },
8647 { 1080 /* bgtu */, 4 /* 2 */, MCK_JumpTarget, AMFBS_None },
8648 { 1080 /* bgtu */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_None },
8649 { 1080 /* bgtu */, 4 /* 2 */, MCK_JumpTarget, AMFBS_None },
8690 { 1267 /* ble */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_None },
8691 { 1267 /* ble */, 4 /* 2 */, MCK_JumpTarget, AMFBS_None },
8692 { 1267 /* ble */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_None },
8693 { 1267 /* ble */, 4 /* 2 */, MCK_JumpTarget, AMFBS_None },
8698 { 1276 /* bleu */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_None },
8699 { 1276 /* bleu */, 4 /* 2 */, MCK_JumpTarget, AMFBS_None },
8700 { 1276 /* bleu */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_None },
8701 { 1276 /* bleu */, 4 /* 2 */, MCK_JumpTarget, AMFBS_None },
8722 { 1312 /* blt */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_None },
8723 { 1312 /* blt */, 4 /* 2 */, MCK_JumpTarget, AMFBS_None },
8724 { 1312 /* blt */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_None },
8725 { 1312 /* blt */, 4 /* 2 */, MCK_JumpTarget, AMFBS_None },
8736 { 1326 /* bltu */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_None },
8737 { 1326 /* bltu */, 4 /* 2 */, MCK_JumpTarget, AMFBS_None },
8738 { 1326 /* bltu */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_None },
8739 { 1326 /* bltu */, 4 /* 2 */, MCK_JumpTarget, AMFBS_None },
8782 { 1419 /* bne */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_None },
8783 { 1419 /* bne */, 4 /* 2 */, MCK_JumpTarget, AMFBS_None },
9545 { 3314 /* dla */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_None },
9546 { 3314 /* dla */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_None },
9547 { 3314 /* dla */, 2 /* 1 */, MCK_Mem, AMFBS_None },
9548 { 3318 /* dli */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_None },
9557 { 3339 /* dmfc2 */, 2 /* 1 */, MCK_COP2AsmReg, AMFBS_None },
9558 { 3339 /* dmfc2 */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_None },
9575 { 3379 /* dmtc2 */, 2 /* 1 */, MCK_COP2AsmReg, AMFBS_None },
9576 { 3379 /* dmtc2 */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_None },
9999 { 5300 /* jal */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_None },
10002 { 5300 /* jal */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_None },
10055 { 5419 /* la */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_None },
10056 { 5419 /* la */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_None },
10057 { 5419 /* la */, 2 /* 1 */, MCK_Mem, AMFBS_None },
10146 { 5561 /* li */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_None },
10147 { 5564 /* li.d */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_None },
10150 { 5569 /* li.s */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_None },
10921 { 7761 /* rol */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_None },
10922 { 7761 /* rol */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_None },
10923 { 7761 /* rol */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_None },
10924 { 7761 /* rol */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_None },
10925 { 7765 /* ror */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_None },
10926 { 7765 /* ror */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_None },
10927 { 7765 /* ror */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_None },
10928 { 7765 /* ror */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_None },
11358 { 9072 /* subu */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_None },
11359 { 9072 /* subu */, 2 /* 1 */, MCK_InvNum, AMFBS_None },
11363 { 9072 /* subu */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_None },
11364 { 9072 /* subu */, 4 /* 2 */, MCK_InvNum, AMFBS_None },
11521 { 9499 /* trunc.w.s */, 3 /* 0, 1 */, MCK_FGR32AsmReg, AMFBS_None },
11522 { 9499 /* trunc.w.s */, 4 /* 2 */, MCK_GPR32AsmReg, AMFBS_None },
11523 { 9509 /* ulh */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_None },
11524 { 9509 /* ulh */, 2 /* 1 */, MCK_Mem, AMFBS_None },
11525 { 9513 /* ulhu */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_None },
11526 { 9513 /* ulhu */, 2 /* 1 */, MCK_Mem, AMFBS_None },
11527 { 9518 /* ulw */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_None },
11528 { 9518 /* ulw */, 2 /* 1 */, MCK_Mem, AMFBS_None },
11529 { 9522 /* ush */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_None },
11530 { 9522 /* ush */, 2 /* 1 */, MCK_Mem, AMFBS_None },
11531 { 9526 /* usw */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_None },
11532 { 9526 /* usw */, 2 /* 1 */, MCK_Mem, AMFBS_None },