|
|
reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
|
References
gen/lib/Target/Mips/MipsGenAsmMatcher.inc 5429 { 45 /* add */, Mips::ADD_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
5434 { 45 /* add */, Mips::ADD_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
5454 { 98 /* addiu */, Mips::ADDIU_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__SImm161_1, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_SImm16 }, },
5459 { 98 /* addiu */, Mips::ADDIU_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm161_2, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_SImm16 }, },
5465 { 104 /* addiupc */, Mips::ADDIUPC_MMR6, Convert__GPR32AsmReg1_0__Simm19_Lsl21_1, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_Simm19_Lsl2 }, },
5499 { 325 /* addu */, Mips::ADDU_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
5505 { 325 /* addu */, Mips::ADDU_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
5515 { 346 /* addu16 */, Mips::ADDU16_MMR6, Convert__GPRMM16AsmReg1_0__GPRMM16AsmReg1_1__GPRMM16AsmReg1_2, AMFBS_InMicroMips_HasMips32r6, { MCK_GPRMM16AsmReg, MCK_GPRMM16AsmReg, MCK_GPRMM16AsmReg }, },
5535 { 459 /* align */, Mips::ALIGN_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__ConstantUImm2_01_3, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm2_0 }, },
5537 { 465 /* aluipc */, Mips::ALUIPC_MMR6, Convert__GPR32AsmReg1_0__SImm161_1, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_SImm16 }, },
5541 { 472 /* and */, Mips::AND_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
5542 { 472 /* and */, Mips::ANDI_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__UImm161_1, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_UImm16 }, },
5548 { 472 /* and */, Mips::AND_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
5549 { 472 /* and */, Mips::ANDI_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__UImm161_2, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_UImm16 }, },
5555 { 482 /* and16 */, Mips::AND16_MMR6, Convert__GPRMM16AsmReg1_0__GPRMM16AsmReg1_1__Tie0_1_1, AMFBS_InMicroMips_HasMips32r6, { MCK_GPRMM16AsmReg, MCK_GPRMM16AsmReg }, },
5556 { 488 /* andi */, Mips::ANDI_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__UImm161_1, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_UImm16 }, },
5559 { 488 /* andi */, Mips::ANDI_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__UImm161_2, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_UImm16 }, },
5564 { 500 /* andi16 */, Mips::ANDI16_MMR6, Convert__GPRMM16AsmReg1_0__GPRMM16AsmReg1_1__Imm1_2, AMFBS_InMicroMips_HasMips32r6, { MCK_GPRMM16AsmReg, MCK_GPRMM16AsmReg, MCK_Imm }, },
5576 { 586 /* aui */, Mips::AUI_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__UImm161_2, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_UImm16 }, },
5578 { 590 /* auipc */, Mips::AUIPC_MMR6, Convert__GPR32AsmReg1_0__SImm161_1, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_SImm16 }, },
5600 { 734 /* b16 */, Mips::BC16_MMR6, Convert__JumpTarget1_0, AMFBS_InMicroMips_HasMips32r6, { MCK_JumpTarget }, },
5608 { 748 /* balc */, Mips::BALC_MMR6, Convert__JumpTarget1_0, AMFBS_InMicroMips_HasMips32r6, { MCK_JumpTarget }, },
5618 { 788 /* bc */, Mips::BC_MMR6, Convert__JumpTarget1_0, AMFBS_InMicroMips_HasMips32r6, { MCK_JumpTarget }, },
5619 { 791 /* bc16 */, Mips::BC16_MMR6, Convert__JumpTarget1_0, AMFBS_InMicroMips_HasMips32r6, { MCK_JumpTarget }, },
5637 { 855 /* bc2eqzc */, Mips::BC2EQZC_MMR6, Convert__COP2AsmReg1_0__JumpTarget1_1, AMFBS_InMicroMips_HasMips32r6, { MCK_COP2AsmReg, MCK_JumpTarget }, },
5639 { 870 /* bc2nezc */, Mips::BC2NEZC_MMR6, Convert__COP2AsmReg1_0__JumpTarget1_1, AMFBS_InMicroMips_HasMips32r6, { MCK_COP2AsmReg, MCK_JumpTarget }, },
5652 { 942 /* beqc */, Mips::BEQC_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__JumpTarget1_2, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_JumpTarget }, },
5661 { 957 /* beqz16 */, Mips::BEQZC16_MMR6, Convert__GPRMM16AsmReg1_0__JumpTarget1_1, AMFBS_InMicroMips_HasMips32r6, { MCK_GPRMM16AsmReg, MCK_JumpTarget }, },
5663 { 964 /* beqzalc */, Mips::BEQZALC_MMR6, Convert__GPR32AsmReg1_0__JumpTarget1_1, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_JumpTarget }, },
5666 { 972 /* beqzc */, Mips::BEQZC_MMR6, Convert__GPR32AsmReg1_0__JumpTarget1_1, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_JumpTarget }, },
5668 { 978 /* beqzc16 */, Mips::BEQZC16_MMR6, Convert__GPRMM16AsmReg1_0__JumpTarget1_1, AMFBS_InMicroMips_HasMips32r6, { MCK_GPRMM16AsmReg, MCK_JumpTarget }, },
5673 { 996 /* bgec */, Mips::BGEC_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__JumpTarget1_2, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_JumpTarget }, },
5680 { 1011 /* bgeuc */, Mips::BGEUC_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__JumpTarget1_2, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_JumpTarget }, },
5689 { 1035 /* bgezalc */, Mips::BGEZALC_MMR6, Convert__GPR32AsmReg1_0__JumpTarget1_1, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_JumpTarget }, },
5693 { 1059 /* bgezc */, Mips::BGEZC_MMR6, Convert__GPR32AsmReg1_0__JumpTarget1_1, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_JumpTarget }, },
5707 { 1096 /* bgtzalc */, Mips::BGTZALC_MMR6, Convert__GPR32AsmReg1_0__JumpTarget1_1, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_JumpTarget }, },
5709 { 1104 /* bgtzc */, Mips::BGTZC_MMR6, Convert__GPR32AsmReg1_0__JumpTarget1_1, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_JumpTarget }, },
5731 { 1259 /* bitswap */, Mips::BITSWAP_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
5743 { 1292 /* blezalc */, Mips::BLEZALC_MMR6, Convert__GPR32AsmReg1_0__JumpTarget1_1, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_JumpTarget }, },
5745 { 1300 /* blezc */, Mips::BLEZC_MMR6, Convert__GPR32AsmReg1_0__JumpTarget1_1, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_JumpTarget }, },
5751 { 1316 /* bltc */, Mips::BLTC_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__JumpTarget1_2, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_JumpTarget }, },
5758 { 1331 /* bltuc */, Mips::BLTUC_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__JumpTarget1_2, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_JumpTarget }, },
5767 { 1355 /* bltzalc */, Mips::BLTZALC_MMR6, Convert__GPR32AsmReg1_0__JumpTarget1_1, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_JumpTarget }, },
5771 { 1379 /* bltzc */, Mips::BLTZC_MMR6, Convert__GPR32AsmReg1_0__JumpTarget1_1, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_JumpTarget }, },
5782 { 1423 /* bnec */, Mips::BNEC_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__JumpTarget1_2, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_JumpTarget }, },
5799 { 1498 /* bnez16 */, Mips::BNEZC16_MMR6, Convert__GPRMM16AsmReg1_0__JumpTarget1_1, AMFBS_InMicroMips_HasMips32r6, { MCK_GPRMM16AsmReg, MCK_JumpTarget }, },
5801 { 1505 /* bnezalc */, Mips::BNEZALC_MMR6, Convert__GPR32AsmReg1_0__JumpTarget1_1, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_JumpTarget }, },
5804 { 1513 /* bnezc */, Mips::BNEZC_MMR6, Convert__GPR32AsmReg1_0__JumpTarget1_1, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_JumpTarget }, },
5806 { 1519 /* bnezc16 */, Mips::BNEZC16_MMR6, Convert__GPRMM16AsmReg1_0__JumpTarget1_1, AMFBS_InMicroMips_HasMips32r6, { MCK_GPRMM16AsmReg, MCK_JumpTarget }, },
5809 { 1533 /* bnvc */, Mips::BNVC_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__JumpTarget1_2, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_JumpTarget }, },
5816 { 1568 /* bovc */, Mips::BOVC_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__JumpTarget1_2, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_JumpTarget }, },
5826 { 1592 /* break */, Mips::BREAK_MMR6, Convert__ConstantUImm10_01_0__ConstantUImm10_01_1, AMFBS_InMicroMips_HasMips32r6, { MCK_ConstantUImm10_0, MCK_ConstantUImm10_0 }, },
5829 { 1598 /* break16 */, Mips::BREAK16_MMR6, Convert__ConstantUImm4_01_0, AMFBS_InMicroMips_HasMips32r6, { MCK_ConstantUImm4_0 }, },
6044 { 1962 /* cache */, Mips::CACHE_MMR6, Convert__Mem2_1__ConstantUImm5_01_0, AMFBS_InMicroMips_HasMips32r6, { MCK_ConstantUImm5_0, MCK_Mem }, },
6078 { 2098 /* class.d */, Mips::CLASS_D_MMR6, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1, AMFBS_InMicroMips_HasMips32r6, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
6080 { 2106 /* class.s */, Mips::CLASS_S_MMR6, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1, AMFBS_InMicroMips_HasMips32r6, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
6098 { 2250 /* clo */, Mips::CLO_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
6118 { 2390 /* clz */, Mips::CLZ_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
6301 { 3186 /* deret */, Mips::DERET_MMR6, Convert_NoOperands, AMFBS_InMicroMips_HasMips32r6, { }, },
6309 { 3209 /* di */, Mips::DI_MMR6, Convert__regZERO, AMFBS_InMicroMips_HasMips32r6, { }, },
6312 { 3209 /* di */, Mips::DI_MMR6, Convert__GPR32AsmReg1_0, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg }, },
6327 { 3229 /* div */, Mips::DIV_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
6354 { 3309 /* divu */, Mips::DIVU_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
6503 { 3937 /* dvp */, Mips::DVP_MMR6, Convert__regZERO, AMFBS_InMicroMips_HasMips32r6, { }, },
6505 { 3937 /* dvp */, Mips::DVP_MMR6, Convert__GPR32AsmReg1_0, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg }, },
6509 { 3946 /* ehb */, Mips::EHB_MMR6, Convert_NoOperands, AMFBS_InMicroMips_HasMips32r6, { }, },
6512 { 3950 /* ei */, Mips::EI_MMR6, Convert__regZERO, AMFBS_InMicroMips_HasMips32r6, { }, },
6515 { 3950 /* ei */, Mips::EI_MMR6, Convert__GPR32AsmReg1_0, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg }, },
6520 { 3957 /* eret */, Mips::ERET_MMR6, Convert_NoOperands, AMFBS_InMicroMips_HasMips32r6, { }, },
6523 { 3962 /* eretnc */, Mips::ERETNC_MMR6, Convert_NoOperands, AMFBS_InMicroMips_HasMips32r6, { }, },
6525 { 3969 /* evp */, Mips::EVP_MMR6, Convert__regZERO, AMFBS_InMicroMips_HasMips32r6, { }, },
6527 { 3969 /* evp */, Mips::EVP_MMR6, Convert__GPR32AsmReg1_0, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg }, },
6532 { 3978 /* ext */, Mips::EXT_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm5_01_2__ConstantUImm5_11_3, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm5_0, MCK_ConstantUImm5_1 }, },
6719 { 5221 /* ins */, Mips::INS_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm5_01_2__ConstantUImm5_11_3__Tie0_1_1, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm5_0, MCK_ConstantUImm5_1 }, },
6737 { 5300 /* jal */, Mips::BALC_MMR6, Convert__JumpTarget1_0, AMFBS_InMicroMips_HasMips32r6, { MCK_JumpTarget }, },
6740 { 5304 /* jalr */, Mips::JALRC16_MMR6, Convert__GPR32AsmReg1_0, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg }, },
6751 { 5317 /* jalrc */, Mips::JALRC_MMR6, Convert__regRA__GPR32AsmReg1_0, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg }, },
6753 { 5317 /* jalrc */, Mips::JALRC_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
6754 { 5323 /* jalrc.hb */, Mips::JALRC_HB_MMR6, Convert__regRA__GPR32AsmReg1_0, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg }, },
6755 { 5323 /* jalrc.hb */, Mips::JALRC_HB_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
6762 { 5356 /* jialc */, Mips::JIALC_MMR6, Convert__GPR32AsmReg1_0__JumpTarget1_1, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_JumpTarget }, },
6765 { 5362 /* jic */, Mips::JIC_MMR6, Convert__GPR32AsmReg1_0__JumpTarget1_1, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_JumpTarget }, },
6784 { 5394 /* jrc16 */, Mips::JRC16_MMR6, Convert__GPR32AsmReg1_0, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg }, },
6785 { 5400 /* jrcaddiusp */, Mips::JRCADDIUSP_MMR6, Convert__UImm5Lsl21_0, AMFBS_InMicroMips_HasMips32r6, { MCK_UImm5Lsl2 }, },
6792 { 5422 /* lapc */, Mips::ADDIUPC_MMR6, Convert__GPR32AsmReg1_0__Simm19_Lsl21_1, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_Simm19_Lsl2 }, },
6793 { 5427 /* lb */, Mips::LB_MMR6, Convert__GPR32AsmReg1_0__MemOffsetSimm162_1, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_MemOffsetSimm16 }, },
6798 { 5434 /* lbu */, Mips::LBU_MMR6, Convert__GPR32AsmReg1_0__MemOffsetSimm162_1, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_MemOffsetSimm16 }, },
6817 { 5482 /* ldc2 */, Mips::LDC2_MMR6, Convert__COP2AsmReg1_0__MemOffsetSimm112_1, AMFBS_InMicroMips_HasMips32r6, { MCK_COP2AsmReg, MCK_MemOffsetSimm11 }, },
6849 { 5574 /* li16 */, Mips::LI16_MMR6, Convert__GPRMM16AsmReg1_0__UImm7_N11_1, AMFBS_InMicroMips_HasMips32r6, { MCK_GPRMM16AsmReg, MCK_UImm7_N1 }, },
6852 { 5579 /* ll */, Mips::LL_MMR6, Convert__GPR32AsmReg1_0__MemOffsetSimm92_1, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_MemOffsetSimm9 }, },
6861 { 5590 /* lsa */, Mips::LSA_MMR6, Convert__GPR32AsmReg1_2__GPR32AsmReg1_1__GPR32AsmReg1_0__ConstantUImm2_11_3, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm2_1 }, },
6863 { 5594 /* lui */, Mips::LUI_MMR6, Convert__GPR32AsmReg1_0__UImm161_1, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_UImm16 }, },
6874 { 5604 /* lw */, Mips::LW_MMR6, Convert__GPR32AsmReg1_0__Mem2_1, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_Mem }, },
6883 { 5617 /* lwc2 */, Mips::LWC2_MMR6, Convert__COP2AsmReg1_0__MemOffsetSimm112_1, AMFBS_InMicroMips_HasMips32r6, { MCK_COP2AsmReg, MCK_MemOffsetSimm11 }, },
6894 { 5644 /* lwm16 */, Mips::LWM16_MMR6, Convert__RegList161_0__MemOffsetUimm42_1, AMFBS_InMicroMips_HasMips32r6, { MCK_RegList16, MCK_MemOffsetUimm4 }, },
6898 { 5660 /* lwpc */, Mips::LWPC_MMR6, Convert__GPR32AsmReg1_0__Simm19_Lsl21_1, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_Simm19_Lsl2 }, },
6973 { 6054 /* mfc0 */, Mips::MFC0_MMR6, Convert__GPR32AsmReg1_0__COP0AsmReg1_1__imm_95_0, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_COP0AsmReg }, },
6975 { 6054 /* mfc0 */, Mips::MFC0_MMR6, Convert__GPR32AsmReg1_0__COP0AsmReg1_1__ConstantUImm3_01_2, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_COP0AsmReg, MCK_ConstantUImm3_0 }, },
6980 { 6064 /* mfc2 */, Mips::MFC2_MMR6, Convert__GPR32AsmReg1_0__COP2AsmReg1_1, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_COP2AsmReg }, },
6987 { 6075 /* mfhc0 */, Mips::MFHC0_MMR6, Convert__GPR32AsmReg1_0__COP0AsmReg1_1__imm_95_0, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_COP0AsmReg }, },
6988 { 6075 /* mfhc0 */, Mips::MFHC0_MMR6, Convert__GPR32AsmReg1_0__COP0AsmReg1_1__ConstantUImm3_01_2, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_COP0AsmReg, MCK_ConstantUImm3_0 }, },
6993 { 6087 /* mfhc2 */, Mips::MFHC2_MMR6, Convert__GPR32AsmReg1_0__COP2AsmReg1_1, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_COP2AsmReg }, },
7052 { 6375 /* mod */, Mips::MOD_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7064 { 6450 /* modu */, Mips::MODU_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7081 { 6479 /* move16 */, Mips::MOVE16_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7083 { 6486 /* movep */, Mips::MOVEP_MMR6, Convert__GPRMM16AsmRegMovePPairFirst1_0__GPRMM16AsmRegMovePPairSecond1_1__GPRMM16AsmRegMoveP1_2__GPRMM16AsmRegMoveP1_3, AMFBS_InMicroMips_HasMips32r6, { MCK_GPRMM16AsmRegMovePPairFirst, MCK_GPRMM16AsmRegMovePPairSecond, MCK_GPRMM16AsmRegMoveP, MCK_GPRMM16AsmRegMoveP }, },
7138 { 6679 /* mtc0 */, Mips::MTC0_MMR6, Convert__COP0AsmReg1_1__GPR32AsmReg1_0__imm_95_0, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_COP0AsmReg }, },
7140 { 6679 /* mtc0 */, Mips::MTC0_MMR6, Convert__COP0AsmReg1_1__GPR32AsmReg1_0__ConstantUImm3_01_2, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_COP0AsmReg, MCK_ConstantUImm3_0 }, },
7146 { 6689 /* mtc2 */, Mips::MTC2_MMR6, Convert__COP2AsmReg1_1__GPR32AsmReg1_0, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_COP2AsmReg }, },
7153 { 6700 /* mthc0 */, Mips::MTHC0_MMR6, Convert__COP0AsmReg1_1__GPR32AsmReg1_0__imm_95_0, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_COP0AsmReg }, },
7154 { 6700 /* mthc0 */, Mips::MTHC0_MMR6, Convert__COP0AsmReg1_1__GPR32AsmReg1_0__ConstantUImm3_01_2, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_COP0AsmReg, MCK_ConstantUImm3_0 }, },
7159 { 6712 /* mthc2 */, Mips::MTHC2_MMR6, Convert__COP2AsmReg1_1__GPR32AsmReg1_0, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_COP2AsmReg }, },
7193 { 6829 /* muh */, Mips::MUH_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7195 { 6829 /* muh */, Mips::MUH_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7196 { 6833 /* muhu */, Mips::MUHU_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7198 { 6833 /* muhu */, Mips::MUHU_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7201 { 6838 /* mul */, Mips::MUL_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7205 { 6838 /* mul */, Mips::MUL_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7254 { 7049 /* mulu */, Mips::MULU_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7256 { 7049 /* mulu */, Mips::MULU_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7263 { 7082 /* neg */, Mips::SUB_MMR6, Convert__GPR32AsmReg1_0__regZERO__GPR32AsmReg1_0, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg }, },
7267 { 7082 /* neg */, Mips::SUB_MMR6, Convert__GPR32AsmReg1_0__regZERO__GPR32AsmReg1_1, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7277 { 7098 /* negu */, Mips::SUBU_MMR6, Convert__GPR32AsmReg1_0__regZERO__GPR32AsmReg1_0, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg }, },
7280 { 7098 /* negu */, Mips::SUBU_MMR6, Convert__GPR32AsmReg1_0__regZERO__GPR32AsmReg1_1, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7300 { 7191 /* nop */, Mips::SLL_MMR6, Convert__regZERO__regZERO__imm_95_0, AMFBS_InMicroMips_HasMips32r6, { }, },
7308 { 7195 /* nor */, Mips::NOR_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7315 { 7212 /* not */, Mips::NOR_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__regZERO, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg }, },
7319 { 7212 /* not */, Mips::NOR_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__regZERO, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7321 { 7216 /* not16 */, Mips::NOT16_MMR6, Convert__GPRMM16AsmReg1_0__GPRMM16AsmReg1_1, AMFBS_InMicroMips_HasMips32r6, { MCK_GPRMM16AsmReg, MCK_GPRMM16AsmReg }, },
7325 { 7222 /* or */, Mips::OR_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7326 { 7222 /* or */, Mips::ORI_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__UImm161_1, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_UImm16 }, },
7332 { 7222 /* or */, Mips::OR_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7333 { 7222 /* or */, Mips::ORI_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__UImm161_2, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_UImm16 }, },
7339 { 7230 /* or16 */, Mips::OR16_MMR6, Convert__GPRMM16AsmReg1_0__GPRMM16AsmReg1_1__Tie0_1_1, AMFBS_InMicroMips_HasMips32r6, { MCK_GPRMM16AsmReg, MCK_GPRMM16AsmReg }, },
7340 { 7235 /* ori */, Mips::ORI_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__UImm161_1, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_UImm16 }, },
7343 { 7235 /* ori */, Mips::ORI_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__UImm161_2, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_UImm16 }, },
7350 { 7255 /* pause */, Mips::PAUSE_MMR6, Convert_NoOperands, AMFBS_InMicroMips_HasMips32r6, { }, },
7409 { 7633 /* pref */, Mips::PREF_MMR6, Convert__Mem2_1__ConstantUImm5_01_0, AMFBS_InMicroMips_HasMips32r6, { MCK_ConstantUImm5_0, MCK_Mem }, },
7421 { 7675 /* rdhwr */, Mips::RDHWR_MMR6, Convert__GPR32AsmReg1_0__HWRegsAsmReg1_1__imm_95_0, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_HWRegsAsmReg }, },
7423 { 7675 /* rdhwr */, Mips::RDHWR_MMR6, Convert__GPR32AsmReg1_0__HWRegsAsmReg1_1__ConstantUImm3_01_2, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_HWRegsAsmReg, MCK_ConstantUImm3_0 }, },
7426 { 7681 /* rdpgpr */, Mips::RDPGPR_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7450 { 7747 /* rint.d */, Mips::RINT_D_MMR6, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1, AMFBS_InMicroMips_HasMips32r6, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
7452 { 7754 /* rint.s */, Mips::RINT_S_MMR6, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1, AMFBS_InMicroMips_HasMips32r6, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
7499 { 7908 /* sb */, Mips::SB_MMR6, Convert__GPR32AsmReg1_0__Mem2_1, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_Mem }, },
7503 { 7911 /* sb16 */, Mips::SB16_MMR6, Convert__GPRMM16AsmRegZero1_0__MicroMipsMem2_1, AMFBS_InMicroMips_HasMips32r6, { MCK_GPRMM16AsmRegZero, MCK_MicroMipsMem }, },
7508 { 7920 /* sc */, Mips::SC_MMR6, Convert__GPR32AsmReg1_0__Tie0_1_1__MemOffsetSimm92_1, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_MemOffsetSimm9 }, },
7520 { 7934 /* sdbbp */, Mips::SDBBP_MMR6, Convert__imm_95_0, AMFBS_InMicroMips_HasMips32r6, { }, },
7524 { 7934 /* sdbbp */, Mips::SDBBP_MMR6, Convert__ConstantUImm20_01_0, AMFBS_InMicroMips_HasMips32r6, { MCK_ConstantUImm20_0 }, },
7526 { 7940 /* sdbbp16 */, Mips::SDBBP16_MMR6, Convert__ConstantUImm4_01_0, AMFBS_InMicroMips_HasMips32r6, { MCK_ConstantUImm4_0 }, },
7532 { 7953 /* sdc2 */, Mips::SDC2_MMR6, Convert__COP2AsmReg1_0__MemOffsetSimm112_1, AMFBS_InMicroMips_HasMips32r6, { MCK_COP2AsmReg, MCK_MemOffsetSimm11 }, },
7550 { 7985 /* sel.d */, Mips::SEL_D_MMR6, Convert__FGR64AsmReg1_0__Tie0_1_1__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_InMicroMips_HasMips32r6, { MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
7552 { 7991 /* sel.s */, Mips::SEL_S_MMR6, Convert__FGR32AsmReg1_0__Tie0_1_1__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_InMicroMips_HasMips32r6, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
7554 { 7997 /* seleqz */, Mips::SELEQZ_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7557 { 8004 /* seleqz.d */, Mips::SELEQZ_D_MMR6, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_InMicroMips_HasMips32r6, { MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
7559 { 8013 /* seleqz.s */, Mips::SELEQZ_S_MMR6, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_InMicroMips_HasMips32r6, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
7561 { 8022 /* selnez */, Mips::SELNEZ_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7564 { 8029 /* selnez.d */, Mips::SELNEZ_D_MMR6, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_InMicroMips_HasMips32r6, { MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
7566 { 8038 /* selnez.s */, Mips::SELNEZ_S_MMR6, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_InMicroMips_HasMips32r6, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
7604 { 8074 /* sh */, Mips::SH_MMR6, Convert__GPR32AsmReg1_0__Mem2_1, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_Mem }, },
7608 { 8077 /* sh16 */, Mips::SH16_MMR6, Convert__GPRMM16AsmRegZero1_0__MicroMipsMem2_1, AMFBS_InMicroMips_HasMips32r6, { MCK_GPRMM16AsmRegZero, MCK_MicroMipsMem }, },
7663 { 8320 /* sigrie */, Mips::SIGRIE_MMR6, Convert__imm_95_0, AMFBS_InMicroMips_HasMips32r6, { }, },
7665 { 8320 /* sigrie */, Mips::SIGRIE_MMR6, Convert__UImm161_0, AMFBS_InMicroMips_HasMips32r6, { MCK_UImm16 }, },
7677 { 8379 /* sll */, Mips::SLL_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__ConstantUImm5_01_1, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_ConstantUImm5_0 }, },
7684 { 8379 /* sll */, Mips::SLL_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm5_01_2, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm5_0 }, },
7691 { 8407 /* sll16 */, Mips::SLL16_MMR6, Convert__GPRMM16AsmReg1_0__GPRMM16AsmReg1_1__Imm1_2, AMFBS_InMicroMips_HasMips32r6, { MCK_GPRMM16AsmReg, MCK_GPRMM16AsmReg, MCK_Imm }, },
7787 { 8706 /* srl16 */, Mips::SRL16_MMR6, Convert__GPRMM16AsmReg1_0__GPRMM16AsmReg1_1__Imm1_2, AMFBS_InMicroMips_HasMips32r6, { MCK_GPRMM16AsmReg, MCK_GPRMM16AsmReg, MCK_Imm }, },
7804 { 8805 /* ssnop */, Mips::SSNOP_MMR6, Convert_NoOperands, AMFBS_InMicroMips_HasMips32r6, { }, },
7812 { 8831 /* sub */, Mips::SUB_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7816 { 8831 /* sub */, Mips::SUB_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7855 { 9072 /* subu */, Mips::SUBU_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7860 { 9072 /* subu */, Mips::SUBU_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7869 { 9093 /* subu16 */, Mips::SUBU16_MMR6, Convert__GPRMM16AsmReg1_0__GPRMM16AsmReg1_1__GPRMM16AsmReg1_2, AMFBS_InMicroMips_HasMips32r6, { MCK_GPRMM16AsmReg, MCK_GPRMM16AsmReg, MCK_GPRMM16AsmReg }, },
7889 { 9206 /* sw */, Mips::SWSP_MMR6, Convert__GPR32AsmReg1_0__MicroMipsMemSP2_1, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_MicroMipsMemSP }, },
7894 { 9206 /* sw */, Mips::SW_MMR6, Convert__GPR32AsmReg1_0__Mem2_1, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_Mem }, },
7899 { 9209 /* sw16 */, Mips::SW16_MMR6, Convert__GPRMM16AsmRegZero1_0__MicroMipsMem2_1, AMFBS_InMicroMips_HasMips32r6, { MCK_GPRMM16AsmRegZero, MCK_MicroMipsMem }, },
7903 { 9219 /* swc2 */, Mips::SWC2_MMR6, Convert__COP2AsmReg1_0__MemOffsetSimm112_1, AMFBS_InMicroMips_HasMips32r6, { MCK_COP2AsmReg, MCK_MemOffsetSimm11 }, },
7914 { 9246 /* swm16 */, Mips::SWM16_MMR6, Convert__RegList161_0__MemOffsetUimm42_1, AMFBS_InMicroMips_HasMips32r6, { MCK_RegList16, MCK_MemOffsetUimm4 }, },
7925 { 9282 /* sync */, Mips::SYNC_MMR6, Convert__imm_95_0, AMFBS_InMicroMips_HasMips32r6, { }, },
7928 { 9282 /* sync */, Mips::SYNC_MMR6, Convert__ConstantUImm5_01_0, AMFBS_InMicroMips_HasMips32r6, { MCK_ConstantUImm5_0 }, },
7932 { 9287 /* synci */, Mips::SYNCI_MMR6, Convert__MemOffsetSimm162_0, AMFBS_InMicroMips_HasMips32r6, { MCK_MemOffsetSimm16 }, },
7972 { 9403 /* tlbinv */, Mips::TLBINV_MMR6, Convert_NoOperands, AMFBS_InMicroMips_HasMips32r6, { }, },
7974 { 9410 /* tlbinvf */, Mips::TLBINVF_MMR6, Convert_NoOperands, AMFBS_InMicroMips_HasMips32r6, { }, },
8032 { 9576 /* wait */, Mips::WAIT_MMR6, Convert__ConstantUImm10_01_0, AMFBS_InMicroMips_HasMips32r6, { MCK_ConstantUImm10_0 }, },
8038 { 9587 /* wrpgpr */, Mips::WRPGPR_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
8040 { 9594 /* wsbh */, Mips::WSBH_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
8045 { 9599 /* xor */, Mips::XOR_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
8046 { 9599 /* xor */, Mips::XORI_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__UImm161_1, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_UImm16 }, },
8052 { 9599 /* xor */, Mips::XOR_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
8053 { 9599 /* xor */, Mips::XORI_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__UImm161_2, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_UImm16 }, },
8059 { 9609 /* xor16 */, Mips::XOR16_MMR6, Convert__GPRMM16AsmReg1_0__GPRMM16AsmReg1_1__Tie0_1_1, AMFBS_InMicroMips_HasMips32r6, { MCK_GPRMM16AsmReg, MCK_GPRMM16AsmReg }, },
8060 { 9615 /* xori */, Mips::XORI_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__UImm161_1, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_UImm16 }, },
8063 { 9615 /* xori */, Mips::XORI_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__UImm161_2, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_UImm16 }, },
8314 { 45 /* add */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 },
8319 { 45 /* add */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 },
8337 { 98 /* addiu */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 },
8340 { 98 /* addiu */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 },
8344 { 104 /* addiupc */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 },
8377 { 325 /* addu */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 },
8382 { 325 /* addu */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 },
8392 { 346 /* addu16 */, 7 /* 0, 1, 2 */, MCK_GPRMM16AsmReg, AMFBS_InMicroMips_HasMips32r6 },
8412 { 459 /* align */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 },
8414 { 465 /* aluipc */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 },
8417 { 472 /* and */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 },
8418 { 472 /* and */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 },
8424 { 472 /* and */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 },
8425 { 472 /* and */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 },
8431 { 482 /* and16 */, 3 /* 0, 1 */, MCK_GPRMM16AsmReg, AMFBS_InMicroMips_HasMips32r6 },
8432 { 488 /* andi */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 },
8435 { 488 /* andi */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 },
8440 { 500 /* andi16 */, 3 /* 0, 1 */, MCK_GPRMM16AsmReg, AMFBS_InMicroMips_HasMips32r6 },
8452 { 586 /* aui */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 },
8454 { 590 /* auipc */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 },
8476 { 734 /* b16 */, 1 /* 0 */, MCK_JumpTarget, AMFBS_InMicroMips_HasMips32r6 },
8484 { 748 /* balc */, 1 /* 0 */, MCK_JumpTarget, AMFBS_InMicroMips_HasMips32r6 },
8500 { 788 /* bc */, 1 /* 0 */, MCK_JumpTarget, AMFBS_InMicroMips_HasMips32r6 },
8501 { 791 /* bc16 */, 1 /* 0 */, MCK_JumpTarget, AMFBS_InMicroMips_HasMips32r6 },
8530 { 855 /* bc2eqzc */, 1 /* 0 */, MCK_COP2AsmReg, AMFBS_InMicroMips_HasMips32r6 },
8531 { 855 /* bc2eqzc */, 2 /* 1 */, MCK_JumpTarget, AMFBS_InMicroMips_HasMips32r6 },
8534 { 870 /* bc2nezc */, 1 /* 0 */, MCK_COP2AsmReg, AMFBS_InMicroMips_HasMips32r6 },
8535 { 870 /* bc2nezc */, 2 /* 1 */, MCK_JumpTarget, AMFBS_InMicroMips_HasMips32r6 },
8552 { 942 /* beqc */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 },
8553 { 942 /* beqc */, 4 /* 2 */, MCK_JumpTarget, AMFBS_InMicroMips_HasMips32r6 },
8568 { 957 /* beqz16 */, 1 /* 0 */, MCK_GPRMM16AsmReg, AMFBS_InMicroMips_HasMips32r6 },
8569 { 957 /* beqz16 */, 2 /* 1 */, MCK_JumpTarget, AMFBS_InMicroMips_HasMips32r6 },
8572 { 964 /* beqzalc */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 },
8573 { 964 /* beqzalc */, 2 /* 1 */, MCK_JumpTarget, AMFBS_InMicroMips_HasMips32r6 },
8578 { 972 /* beqzc */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 },
8579 { 972 /* beqzc */, 2 /* 1 */, MCK_JumpTarget, AMFBS_InMicroMips_HasMips32r6 },
8582 { 978 /* beqzc16 */, 1 /* 0 */, MCK_GPRMM16AsmReg, AMFBS_InMicroMips_HasMips32r6 },
8583 { 978 /* beqzc16 */, 2 /* 1 */, MCK_JumpTarget, AMFBS_InMicroMips_HasMips32r6 },
8592 { 996 /* bgec */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 },
8593 { 996 /* bgec */, 4 /* 2 */, MCK_JumpTarget, AMFBS_InMicroMips_HasMips32r6 },
8606 { 1011 /* bgeuc */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 },
8607 { 1011 /* bgeuc */, 4 /* 2 */, MCK_JumpTarget, AMFBS_InMicroMips_HasMips32r6 },
8624 { 1035 /* bgezalc */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 },
8625 { 1035 /* bgezalc */, 2 /* 1 */, MCK_JumpTarget, AMFBS_InMicroMips_HasMips32r6 },
8632 { 1059 /* bgezc */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 },
8633 { 1059 /* bgezc */, 2 /* 1 */, MCK_JumpTarget, AMFBS_InMicroMips_HasMips32r6 },
8660 { 1096 /* bgtzalc */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 },
8661 { 1096 /* bgtzalc */, 2 /* 1 */, MCK_JumpTarget, AMFBS_InMicroMips_HasMips32r6 },
8664 { 1104 /* bgtzc */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 },
8665 { 1104 /* bgtzc */, 2 /* 1 */, MCK_JumpTarget, AMFBS_InMicroMips_HasMips32r6 },
8689 { 1259 /* bitswap */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 },
8712 { 1292 /* blezalc */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 },
8713 { 1292 /* blezalc */, 2 /* 1 */, MCK_JumpTarget, AMFBS_InMicroMips_HasMips32r6 },
8716 { 1300 /* blezc */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 },
8717 { 1300 /* blezc */, 2 /* 1 */, MCK_JumpTarget, AMFBS_InMicroMips_HasMips32r6 },
8728 { 1316 /* bltc */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 },
8729 { 1316 /* bltc */, 4 /* 2 */, MCK_JumpTarget, AMFBS_InMicroMips_HasMips32r6 },
8742 { 1331 /* bltuc */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 },
8743 { 1331 /* bltuc */, 4 /* 2 */, MCK_JumpTarget, AMFBS_InMicroMips_HasMips32r6 },
8760 { 1355 /* bltzalc */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 },
8761 { 1355 /* bltzalc */, 2 /* 1 */, MCK_JumpTarget, AMFBS_InMicroMips_HasMips32r6 },
8768 { 1379 /* bltzc */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 },
8769 { 1379 /* bltzc */, 2 /* 1 */, MCK_JumpTarget, AMFBS_InMicroMips_HasMips32r6 },
8786 { 1423 /* bnec */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 },
8787 { 1423 /* bnec */, 4 /* 2 */, MCK_JumpTarget, AMFBS_InMicroMips_HasMips32r6 },
8810 { 1498 /* bnez16 */, 1 /* 0 */, MCK_GPRMM16AsmReg, AMFBS_InMicroMips_HasMips32r6 },
8811 { 1498 /* bnez16 */, 2 /* 1 */, MCK_JumpTarget, AMFBS_InMicroMips_HasMips32r6 },
8814 { 1505 /* bnezalc */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 },
8815 { 1505 /* bnezalc */, 2 /* 1 */, MCK_JumpTarget, AMFBS_InMicroMips_HasMips32r6 },
8820 { 1513 /* bnezc */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 },
8821 { 1513 /* bnezc */, 2 /* 1 */, MCK_JumpTarget, AMFBS_InMicroMips_HasMips32r6 },
8824 { 1519 /* bnezc16 */, 1 /* 0 */, MCK_GPRMM16AsmReg, AMFBS_InMicroMips_HasMips32r6 },
8825 { 1519 /* bnezc16 */, 2 /* 1 */, MCK_JumpTarget, AMFBS_InMicroMips_HasMips32r6 },
8830 { 1533 /* bnvc */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 },
8831 { 1533 /* bnvc */, 4 /* 2 */, MCK_JumpTarget, AMFBS_InMicroMips_HasMips32r6 },
8844 { 1568 /* bovc */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 },
8845 { 1568 /* bovc */, 4 /* 2 */, MCK_JumpTarget, AMFBS_InMicroMips_HasMips32r6 },
9160 { 1962 /* cache */, 2 /* 1 */, MCK_Mem, AMFBS_InMicroMips_HasMips32r6 },
9205 { 2098 /* class.d */, 3 /* 0, 1 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_HasMips32r6 },
9207 { 2106 /* class.s */, 3 /* 0, 1 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_HasMips32r6 },
9225 { 2250 /* clo */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 },
9245 { 2390 /* clz */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 },
9498 { 3209 /* di */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 },
9514 { 3229 /* div */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 },
9543 { 3309 /* divu */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 },
9753 { 3937 /* dvp */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 },
9756 { 3950 /* ei */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 },
9760 { 3969 /* evp */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 },
9764 { 3978 /* ext */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 },
9981 { 5221 /* ins */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 },
10001 { 5300 /* jal */, 1 /* 0 */, MCK_JumpTarget, AMFBS_InMicroMips_HasMips32r6 },
10004 { 5304 /* jalr */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 },
10014 { 5317 /* jalrc */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 },
10016 { 5317 /* jalrc */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 },
10017 { 5323 /* jalrc.hb */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 },
10018 { 5323 /* jalrc.hb */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 },
10025 { 5356 /* jialc */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 },
10026 { 5356 /* jialc */, 2 /* 1 */, MCK_JumpTarget, AMFBS_InMicroMips_HasMips32r6 },
10031 { 5362 /* jic */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 },
10032 { 5362 /* jic */, 2 /* 1 */, MCK_JumpTarget, AMFBS_InMicroMips_HasMips32r6 },
10048 { 5394 /* jrc16 */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 },
10059 { 5422 /* lapc */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 },
10060 { 5427 /* lb */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 },
10061 { 5427 /* lb */, 2 /* 1 */, MCK_MemOffsetSimm16, AMFBS_InMicroMips_HasMips32r6 },
10070 { 5434 /* lbu */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 },
10071 { 5434 /* lbu */, 2 /* 1 */, MCK_MemOffsetSimm16, AMFBS_InMicroMips_HasMips32r6 },
10106 { 5482 /* ldc2 */, 1 /* 0 */, MCK_COP2AsmReg, AMFBS_InMicroMips_HasMips32r6 },
10107 { 5482 /* ldc2 */, 2 /* 1 */, MCK_MemOffsetSimm11, AMFBS_InMicroMips_HasMips32r6 },
10153 { 5574 /* li16 */, 1 /* 0 */, MCK_GPRMM16AsmReg, AMFBS_InMicroMips_HasMips32r6 },
10158 { 5579 /* ll */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 },
10159 { 5579 /* ll */, 2 /* 1 */, MCK_MemOffsetSimm9, AMFBS_InMicroMips_HasMips32r6 },
10175 { 5590 /* lsa */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 },
10177 { 5594 /* lui */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 },
10194 { 5604 /* lw */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 },
10195 { 5604 /* lw */, 2 /* 1 */, MCK_Mem, AMFBS_InMicroMips_HasMips32r6 },
10208 { 5617 /* lwc2 */, 1 /* 0 */, MCK_COP2AsmReg, AMFBS_InMicroMips_HasMips32r6 },
10209 { 5617 /* lwc2 */, 2 /* 1 */, MCK_MemOffsetSimm11, AMFBS_InMicroMips_HasMips32r6 },
10230 { 5644 /* lwm16 */, 2 /* 1 */, MCK_MemOffsetUimm4, AMFBS_InMicroMips_HasMips32r6 },
10231 { 5644 /* lwm16 */, 1 /* 0 */, MCK_RegList16, AMFBS_InMicroMips_HasMips32r6 },
10237 { 5660 /* lwpc */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 },
10333 { 6054 /* mfc0 */, 2 /* 1 */, MCK_COP0AsmReg, AMFBS_InMicroMips_HasMips32r6 },
10334 { 6054 /* mfc0 */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 },
10337 { 6054 /* mfc0 */, 2 /* 1 */, MCK_COP0AsmReg, AMFBS_InMicroMips_HasMips32r6 },
10338 { 6054 /* mfc0 */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 },
10347 { 6064 /* mfc2 */, 2 /* 1 */, MCK_COP2AsmReg, AMFBS_InMicroMips_HasMips32r6 },
10348 { 6064 /* mfc2 */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 },
10361 { 6075 /* mfhc0 */, 2 /* 1 */, MCK_COP0AsmReg, AMFBS_InMicroMips_HasMips32r6 },
10362 { 6075 /* mfhc0 */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 },
10363 { 6075 /* mfhc0 */, 2 /* 1 */, MCK_COP0AsmReg, AMFBS_InMicroMips_HasMips32r6 },
10364 { 6075 /* mfhc0 */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 },
10373 { 6087 /* mfhc2 */, 2 /* 1 */, MCK_COP2AsmReg, AMFBS_InMicroMips_HasMips32r6 },
10374 { 6087 /* mfhc2 */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 },
10446 { 6375 /* mod */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 },
10458 { 6450 /* modu */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 },
10473 { 6479 /* move16 */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 },
10477 { 6486 /* movep */, 12 /* 2, 3 */, MCK_GPRMM16AsmRegMoveP, AMFBS_InMicroMips_HasMips32r6 },
10478 { 6486 /* movep */, 1 /* 0 */, MCK_GPRMM16AsmRegMovePPairFirst, AMFBS_InMicroMips_HasMips32r6 },
10479 { 6486 /* movep */, 2 /* 1 */, MCK_GPRMM16AsmRegMovePPairSecond, AMFBS_InMicroMips_HasMips32r6 },
10563 { 6679 /* mtc0 */, 2 /* 1 */, MCK_COP0AsmReg, AMFBS_InMicroMips_HasMips32r6 },
10564 { 6679 /* mtc0 */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 },
10567 { 6679 /* mtc0 */, 2 /* 1 */, MCK_COP0AsmReg, AMFBS_InMicroMips_HasMips32r6 },
10568 { 6679 /* mtc0 */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 },
10579 { 6689 /* mtc2 */, 2 /* 1 */, MCK_COP2AsmReg, AMFBS_InMicroMips_HasMips32r6 },
10580 { 6689 /* mtc2 */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 },
10593 { 6700 /* mthc0 */, 2 /* 1 */, MCK_COP0AsmReg, AMFBS_InMicroMips_HasMips32r6 },
10594 { 6700 /* mthc0 */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 },
10595 { 6700 /* mthc0 */, 2 /* 1 */, MCK_COP0AsmReg, AMFBS_InMicroMips_HasMips32r6 },
10596 { 6700 /* mthc0 */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 },
10605 { 6712 /* mthc2 */, 2 /* 1 */, MCK_COP2AsmReg, AMFBS_InMicroMips_HasMips32r6 },
10606 { 6712 /* mthc2 */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 },
10657 { 6829 /* muh */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 },
10659 { 6829 /* muh */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 },
10660 { 6833 /* muhu */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 },
10662 { 6833 /* muhu */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 },
10665 { 6838 /* mul */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 },
10669 { 6838 /* mul */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 },
10726 { 7049 /* mulu */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 },
10728 { 7049 /* mulu */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 },
10735 { 7082 /* neg */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 },
10738 { 7082 /* neg */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 },
10748 { 7098 /* negu */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 },
10751 { 7098 /* negu */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 },
10774 { 7195 /* nor */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 },
10781 { 7212 /* not */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 },
10784 { 7212 /* not */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 },
10786 { 7216 /* not16 */, 3 /* 0, 1 */, MCK_GPRMM16AsmReg, AMFBS_InMicroMips_HasMips32r6 },
10789 { 7222 /* or */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 },
10790 { 7222 /* or */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 },
10796 { 7222 /* or */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 },
10797 { 7222 /* or */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 },
10803 { 7230 /* or16 */, 3 /* 0, 1 */, MCK_GPRMM16AsmReg, AMFBS_InMicroMips_HasMips32r6 },
10804 { 7235 /* ori */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 },
10807 { 7235 /* ori */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 },
10870 { 7633 /* pref */, 2 /* 1 */, MCK_Mem, AMFBS_InMicroMips_HasMips32r6 },
10884 { 7675 /* rdhwr */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 },
10885 { 7675 /* rdhwr */, 2 /* 1 */, MCK_HWRegsAsmReg, AMFBS_InMicroMips_HasMips32r6 },
10888 { 7675 /* rdhwr */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 },
10889 { 7675 /* rdhwr */, 2 /* 1 */, MCK_HWRegsAsmReg, AMFBS_InMicroMips_HasMips32r6 },
10894 { 7681 /* rdpgpr */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 },
10918 { 7747 /* rint.d */, 3 /* 0, 1 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_HasMips32r6 },
10920 { 7754 /* rint.s */, 3 /* 0, 1 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_HasMips32r6 },
10978 { 7908 /* sb */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 },
10979 { 7908 /* sb */, 2 /* 1 */, MCK_Mem, AMFBS_InMicroMips_HasMips32r6 },
10984 { 7911 /* sb16 */, 1 /* 0 */, MCK_GPRMM16AsmRegZero, AMFBS_InMicroMips_HasMips32r6 },
10985 { 7911 /* sb16 */, 2 /* 1 */, MCK_MicroMipsMem, AMFBS_InMicroMips_HasMips32r6 },
10994 { 7920 /* sc */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 },
10995 { 7920 /* sc */, 2 /* 1 */, MCK_MemOffsetSimm9, AMFBS_InMicroMips_HasMips32r6 },
11024 { 7953 /* sdc2 */, 1 /* 0 */, MCK_COP2AsmReg, AMFBS_InMicroMips_HasMips32r6 },
11025 { 7953 /* sdc2 */, 2 /* 1 */, MCK_MemOffsetSimm11, AMFBS_InMicroMips_HasMips32r6 },
11047 { 7985 /* sel.d */, 7 /* 0, 1, 2 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_HasMips32r6 },
11049 { 7991 /* sel.s */, 7 /* 0, 1, 2 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_HasMips32r6 },
11051 { 7997 /* seleqz */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 },
11054 { 8004 /* seleqz.d */, 7 /* 0, 1, 2 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_HasMips32r6 },
11056 { 8013 /* seleqz.s */, 7 /* 0, 1, 2 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_HasMips32r6 },
11058 { 8022 /* selnez */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 },
11061 { 8029 /* selnez.d */, 7 /* 0, 1, 2 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_HasMips32r6 },
11063 { 8038 /* selnez.s */, 7 /* 0, 1, 2 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_HasMips32r6 },
11102 { 8074 /* sh */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 },
11103 { 8074 /* sh */, 2 /* 1 */, MCK_Mem, AMFBS_InMicroMips_HasMips32r6 },
11108 { 8077 /* sh16 */, 1 /* 0 */, MCK_GPRMM16AsmRegZero, AMFBS_InMicroMips_HasMips32r6 },
11109 { 8077 /* sh16 */, 2 /* 1 */, MCK_MicroMipsMem, AMFBS_InMicroMips_HasMips32r6 },
11182 { 8379 /* sll */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 },
11188 { 8379 /* sll */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 },
11195 { 8407 /* sll16 */, 3 /* 0, 1 */, MCK_GPRMM16AsmReg, AMFBS_InMicroMips_HasMips32r6 },
11285 { 8706 /* srl16 */, 3 /* 0, 1 */, MCK_GPRMM16AsmReg, AMFBS_InMicroMips_HasMips32r6 },
11310 { 8831 /* sub */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 },
11315 { 8831 /* sub */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 },
11355 { 9072 /* subu */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 },
11360 { 9072 /* subu */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 },
11370 { 9093 /* subu16 */, 7 /* 0, 1, 2 */, MCK_GPRMM16AsmReg, AMFBS_InMicroMips_HasMips32r6 },
11393 { 9206 /* sw */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 },
11394 { 9206 /* sw */, 2 /* 1 */, MCK_MicroMipsMemSP, AMFBS_InMicroMips_HasMips32r6 },
11403 { 9206 /* sw */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 },
11404 { 9206 /* sw */, 2 /* 1 */, MCK_Mem, AMFBS_InMicroMips_HasMips32r6 },
11409 { 9209 /* sw16 */, 1 /* 0 */, MCK_GPRMM16AsmRegZero, AMFBS_InMicroMips_HasMips32r6 },
11410 { 9209 /* sw16 */, 2 /* 1 */, MCK_MicroMipsMem, AMFBS_InMicroMips_HasMips32r6 },
11417 { 9219 /* swc2 */, 1 /* 0 */, MCK_COP2AsmReg, AMFBS_InMicroMips_HasMips32r6 },
11418 { 9219 /* swc2 */, 2 /* 1 */, MCK_MemOffsetSimm11, AMFBS_InMicroMips_HasMips32r6 },
11439 { 9246 /* swm16 */, 2 /* 1 */, MCK_MemOffsetUimm4, AMFBS_InMicroMips_HasMips32r6 },
11440 { 9246 /* swm16 */, 1 /* 0 */, MCK_RegList16, AMFBS_InMicroMips_HasMips32r6 },
11461 { 9287 /* synci */, 1 /* 0 */, MCK_MemOffsetSimm16, AMFBS_InMicroMips_HasMips32r6 },
11547 { 9587 /* wrpgpr */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 },
11549 { 9594 /* wsbh */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 },
11553 { 9599 /* xor */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 },
11554 { 9599 /* xor */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 },
11560 { 9599 /* xor */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 },
11561 { 9599 /* xor */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 },
11567 { 9609 /* xor16 */, 3 /* 0, 1 */, MCK_GPRMM16AsmReg, AMFBS_InMicroMips_HasMips32r6 },
11568 { 9615 /* xori */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 },
11571 { 9615 /* xori */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 },