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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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References
gen/lib/Target/Mips/MipsGenAsmMatcher.inc 6046 { 1968 /* cachee */, Mips::CACHEE_MM, Convert__MemOffsetSimm92_1__ConstantUImm5_01_0, AMFBS_InMicroMips_HasEVA, { MCK_ConstantUImm5_0, MCK_MemOffsetSimm9 }, },
6797 { 5430 /* lbe */, Mips::LBE_MM, Convert__GPR32AsmReg1_0__Mem2_1, AMFBS_InMicroMips_HasEVA, { MCK_GPR32AsmReg, MCK_Mem }, },
6803 { 5444 /* lbue */, Mips::LBuE_MM, Convert__GPR32AsmReg1_0__Mem2_1, AMFBS_InMicroMips_HasEVA, { MCK_GPR32AsmReg, MCK_Mem }, },
6832 { 5538 /* lhe */, Mips::LHE_MM, Convert__GPR32AsmReg1_0__MemOffsetSimm92_1, AMFBS_InMicroMips_HasEVA, { MCK_GPR32AsmReg, MCK_MemOffsetSimm9 }, },
6837 { 5552 /* lhue */, Mips::LHuE_MM, Convert__GPR32AsmReg1_0__MemOffsetSimm92_1, AMFBS_InMicroMips_HasEVA, { MCK_GPR32AsmReg, MCK_MemOffsetSimm9 }, },
6859 { 5586 /* lle */, Mips::LLE_MM, Convert__GPR32AsmReg1_0__MemOffsetSimm92_1, AMFBS_InMicroMips_HasEVA, { MCK_GPR32AsmReg, MCK_MemOffsetSimm9 }, },
6887 { 5627 /* lwe */, Mips::LWE_MM, Convert__GPR32AsmReg1_0__MemOffsetSimm92_1, AMFBS_InMicroMips_HasEVA, { MCK_GPR32AsmReg, MCK_MemOffsetSimm9 }, },
7411 { 7638 /* prefe */, Mips::PREFE_MM, Convert__MemOffsetSimm92_1__ConstantUImm5_01_0, AMFBS_InMicroMips_HasEVA, { MCK_ConstantUImm5_0, MCK_MemOffsetSimm9 }, },
7505 { 7916 /* sbe */, Mips::SBE_MM, Convert__GPR32AsmReg1_0__MemOffsetSimm92_1, AMFBS_InMicroMips_HasEVA, { MCK_GPR32AsmReg, MCK_MemOffsetSimm9 }, },
7515 { 7927 /* sce */, Mips::SCE_MM, Convert__GPR32AsmReg1_0__Tie0_1_1__MemOffsetSimm92_1, AMFBS_InMicroMips_HasEVA, { MCK_GPR32AsmReg, MCK_MemOffsetSimm9 }, },
7610 { 8082 /* she */, Mips::SHE_MM, Convert__GPR32AsmReg1_0__MemOffsetSimm92_1, AMFBS_InMicroMips_HasEVA, { MCK_GPR32AsmReg, MCK_MemOffsetSimm9 }, },
7907 { 9229 /* swe */, Mips::SWE_MM, Convert__GPR32AsmReg1_0__MemOffsetSimm92_1, AMFBS_InMicroMips_HasEVA, { MCK_GPR32AsmReg, MCK_MemOffsetSimm9 }, },
9162 { 1968 /* cachee */, 2 /* 1 */, MCK_MemOffsetSimm9, AMFBS_InMicroMips_HasEVA },
10068 { 5430 /* lbe */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasEVA },
10069 { 5430 /* lbe */, 2 /* 1 */, MCK_Mem, AMFBS_InMicroMips_HasEVA },
10080 { 5444 /* lbue */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasEVA },
10081 { 5444 /* lbue */, 2 /* 1 */, MCK_Mem, AMFBS_InMicroMips_HasEVA },
10132 { 5538 /* lhe */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasEVA },
10133 { 5538 /* lhe */, 2 /* 1 */, MCK_MemOffsetSimm9, AMFBS_InMicroMips_HasEVA },
10142 { 5552 /* lhue */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasEVA },
10143 { 5552 /* lhue */, 2 /* 1 */, MCK_MemOffsetSimm9, AMFBS_InMicroMips_HasEVA },
10172 { 5586 /* lle */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasEVA },
10173 { 5586 /* lle */, 2 /* 1 */, MCK_MemOffsetSimm9, AMFBS_InMicroMips_HasEVA },
10216 { 5627 /* lwe */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasEVA },
10217 { 5627 /* lwe */, 2 /* 1 */, MCK_MemOffsetSimm9, AMFBS_InMicroMips_HasEVA },
10872 { 7638 /* prefe */, 2 /* 1 */, MCK_MemOffsetSimm9, AMFBS_InMicroMips_HasEVA },
10988 { 7916 /* sbe */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasEVA },
10989 { 7916 /* sbe */, 2 /* 1 */, MCK_MemOffsetSimm9, AMFBS_InMicroMips_HasEVA },
11008 { 7927 /* sce */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasEVA },
11009 { 7927 /* sce */, 2 /* 1 */, MCK_MemOffsetSimm9, AMFBS_InMicroMips_HasEVA },
11112 { 8082 /* she */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasEVA },
11113 { 8082 /* she */, 2 /* 1 */, MCK_MemOffsetSimm9, AMFBS_InMicroMips_HasEVA },
11425 { 9229 /* swe */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasEVA },
11426 { 9229 /* swe */, 2 /* 1 */, MCK_MemOffsetSimm9, AMFBS_InMicroMips_HasEVA },