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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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References
gen/lib/Target/Mips/MipsGenAsmMatcher.inc 5421 { 16 /* absq_s.ph */, Mips::ABSQ_S_PH_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
5425 { 36 /* absq_s.w */, Mips::ABSQ_S_W_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
5471 { 146 /* addq.ph */, Mips::ADDQ_PH_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
5473 { 154 /* addq_s.ph */, Mips::ADDQ_S_PH_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
5475 { 164 /* addq_s.w */, Mips::ADDQ_S_W_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
5497 { 319 /* addsc */, Mips::ADDSC_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
5512 { 338 /* addu.qb */, Mips::ADDU_QB_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
5518 { 363 /* addu_s.qb */, Mips::ADDU_S_QB_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
5532 { 453 /* addwc */, Mips::ADDWC_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
5728 { 1252 /* bitrev */, Mips::BITREV_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
6128 { 2425 /* cmp.eq.ph */, Mips::CMP_EQ_PH_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
6134 { 2453 /* cmp.le.ph */, Mips::CMP_LE_PH_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
6140 { 2481 /* cmp.lt.ph */, Mips::CMP_LT_PH_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
6198 { 2783 /* cmpgu.eq.qb */, Mips::CMPGU_EQ_QB_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
6200 { 2795 /* cmpgu.le.qb */, Mips::CMPGU_LE_QB_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
6202 { 2807 /* cmpgu.lt.qb */, Mips::CMPGU_LT_QB_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
6206 { 2824 /* cmpu.eq.qb */, Mips::CMPU_EQ_QB_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
6208 { 2835 /* cmpu.le.qb */, Mips::CMPU_LE_QB_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
6210 { 2846 /* cmpu.lt.qb */, Mips::CMPU_LT_QB_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
6411 { 3574 /* dpaq_s.w.ph */, Mips::DPAQ_S_W_PH_MM, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, AMFBS_InMicroMips_HasDSP, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
6413 { 3586 /* dpaq_sa.l.w */, Mips::DPAQ_SA_L_W_MM, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, AMFBS_InMicroMips_HasDSP, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
6419 { 3625 /* dpau.h.qbl */, Mips::DPAU_H_QBL_MM, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, AMFBS_InMicroMips_HasDSP, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
6421 { 3636 /* dpau.h.qbr */, Mips::DPAU_H_QBR_MM, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, AMFBS_InMicroMips_HasDSP, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
6429 { 3671 /* dpsq_s.w.ph */, Mips::DPSQ_S_W_PH_MM, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, AMFBS_InMicroMips_HasDSP, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
6431 { 3683 /* dpsq_sa.l.w */, Mips::DPSQ_SA_L_W_MM, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, AMFBS_InMicroMips_HasDSP, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
6437 { 3722 /* dpsu.h.qbl */, Mips::DPSU_H_QBL_MM, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, AMFBS_InMicroMips_HasDSP, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
6439 { 3733 /* dpsu.h.qbr */, Mips::DPSU_H_QBR_MM, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, AMFBS_InMicroMips_HasDSP, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
6533 { 3982 /* extp */, Mips::EXTP_MM, Convert__GPR32AsmReg1_0__ACC64DSPAsmReg1_1__ConstantUImm5_01_2, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_ACC64DSPAsmReg, MCK_ConstantUImm5_0 }, },
6535 { 3987 /* extpdp */, Mips::EXTPDP_MM, Convert__GPR32AsmReg1_0__ACC64DSPAsmReg1_1__ConstantUImm5_01_2, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_ACC64DSPAsmReg, MCK_ConstantUImm5_0 }, },
6537 { 3994 /* extpdpv */, Mips::EXTPDPV_MM, Convert__GPR32AsmReg1_0__ACC64DSPAsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg }, },
6539 { 4002 /* extpv */, Mips::EXTPV_MM, Convert__GPR32AsmReg1_0__ACC64DSPAsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg }, },
6541 { 4008 /* extr.w */, Mips::EXTR_W_MM, Convert__GPR32AsmReg1_0__ACC64DSPAsmReg1_1__ConstantUImm5_01_2, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_ACC64DSPAsmReg, MCK_ConstantUImm5_0 }, },
6543 { 4015 /* extr_r.w */, Mips::EXTR_R_W_MM, Convert__GPR32AsmReg1_0__ACC64DSPAsmReg1_1__ConstantUImm5_01_2, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_ACC64DSPAsmReg, MCK_ConstantUImm5_0 }, },
6545 { 4024 /* extr_rs.w */, Mips::EXTR_RS_W_MM, Convert__GPR32AsmReg1_0__ACC64DSPAsmReg1_1__ConstantUImm5_01_2, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_ACC64DSPAsmReg, MCK_ConstantUImm5_0 }, },
6547 { 4034 /* extr_s.h */, Mips::EXTR_S_H_MM, Convert__GPR32AsmReg1_0__ACC64DSPAsmReg1_1__ConstantUImm5_01_2, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_ACC64DSPAsmReg, MCK_ConstantUImm5_0 }, },
6549 { 4043 /* extrv.w */, Mips::EXTRV_W_MM, Convert__GPR32AsmReg1_0__ACC64DSPAsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg }, },
6551 { 4051 /* extrv_r.w */, Mips::EXTRV_R_W_MM, Convert__GPR32AsmReg1_0__ACC64DSPAsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg }, },
6553 { 4061 /* extrv_rs.w */, Mips::EXTRV_RS_W_MM, Convert__GPR32AsmReg1_0__ACC64DSPAsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg }, },
6555 { 4072 /* extrv_s.h */, Mips::EXTRV_S_H_MM, Convert__GPR32AsmReg1_0__ACC64DSPAsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg }, },
6724 { 5261 /* insv */, Mips::INSV_MM, Convert__GPR32AsmReg1_0__Tie0_1_1__GPR32AsmReg1_1, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
6804 { 5449 /* lbux */, Mips::LBUX_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_3__GPR32AsmReg1_1, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK__40_, MCK_GPR32AsmReg, MCK__41_ }, },
6838 { 5557 /* lhx */, Mips::LHX_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_3__GPR32AsmReg1_1, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK__40_, MCK_GPR32AsmReg, MCK__41_ }, },
6873 { 5604 /* lw */, Mips::LWDSP_MM, Convert__GPR32AsmReg1_0__Mem2_1, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_Mem }, },
6906 { 5684 /* lwx */, Mips::LWX_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_3__GPR32AsmReg1_1, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK__40_, MCK_GPR32AsmReg, MCK__41_ }, },
6913 { 5699 /* madd */, Mips::MADD_DSP_MM, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, AMFBS_InMicroMips_HasDSP, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
6930 { 5772 /* maddu */, Mips::MADDU_DSP_MM, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, AMFBS_InMicroMips_HasDSP, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
6936 { 5810 /* maq_s.w.phl */, Mips::MAQ_S_W_PHL_MM, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, AMFBS_InMicroMips_HasDSP, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
6938 { 5822 /* maq_s.w.phr */, Mips::MAQ_S_W_PHR_MM, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, AMFBS_InMicroMips_HasDSP, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
6940 { 5834 /* maq_sa.w.phl */, Mips::MAQ_SA_W_PHL_MM, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, AMFBS_InMicroMips_HasDSP, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
6942 { 5847 /* maq_sa.w.phr */, Mips::MAQ_SA_W_PHR_MM, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, AMFBS_InMicroMips_HasDSP, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7001 { 6100 /* mfhi */, Mips::MFHI_DSP_MM, Convert__GPR32AsmReg1_0__ACC64DSPAsmReg1_1, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_ACC64DSPAsmReg }, },
7007 { 6112 /* mflo */, Mips::MFLO_DSP_MM, Convert__GPR32AsmReg1_0__ACC64DSPAsmReg1_1, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_ACC64DSPAsmReg }, },
7061 { 6443 /* modsub */, Mips::MODSUB_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7114 { 6568 /* msub */, Mips::MSUB_DSP_MM, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, AMFBS_InMicroMips_HasDSP, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7131 { 6641 /* msubu */, Mips::MSUBU_DSP_MM, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, AMFBS_InMicroMips_HasDSP, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7166 { 6725 /* mthi */, Mips::MTHI_DSP_MM, Convert__HI32DSPAsmReg1_1__GPR32AsmReg1_0, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_HI32DSPAsmReg }, },
7168 { 6730 /* mthlip */, Mips::MTHLIP_MM, Convert__ACC64DSPAsmReg1_1__GPR32AsmReg1_0__Tie0_1_1, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_ACC64DSPAsmReg }, },
7172 { 6737 /* mtlo */, Mips::MTLO_DSP_MM, Convert__LO32DSPAsmReg1_1__GPR32AsmReg1_0, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_LO32DSPAsmReg }, },
7220 { 6886 /* muleq_s.w.phl */, Mips::MULEQ_S_W_PHL_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7222 { 6900 /* muleq_s.w.phr */, Mips::MULEQ_S_W_PHR_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7224 { 6914 /* muleu_s.ph.qbl */, Mips::MULEU_S_PH_QBL_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7226 { 6929 /* muleu_s.ph.qbr */, Mips::MULEU_S_PH_QBR_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7232 { 6955 /* mulq_rs.ph */, Mips::MULQ_RS_PH_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7244 { 7024 /* mulsaq_s.w.ph */, Mips::MULSAQ_S_W_PH_MM, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, AMFBS_InMicroMips_HasDSP, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7248 { 7038 /* mult */, Mips::MULT_DSP_MM, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasDSP, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7252 { 7043 /* multu */, Mips::MULTU_DSP_MM, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasDSP, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7347 { 7245 /* packrl.ph */, Mips::PACKRL_PH_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7364 { 7353 /* pick.ph */, Mips::PICK_PH_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7366 { 7361 /* pick.qb */, Mips::PICK_QB_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7372 { 7387 /* preceq.w.phl */, Mips::PRECEQ_W_PHL_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7374 { 7400 /* preceq.w.phr */, Mips::PRECEQ_W_PHR_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7376 { 7413 /* precequ.ph.qbl */, Mips::PRECEQU_PH_QBL_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7378 { 7428 /* precequ.ph.qbla */, Mips::PRECEQU_PH_QBLA_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7380 { 7444 /* precequ.ph.qbr */, Mips::PRECEQU_PH_QBR_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7382 { 7459 /* precequ.ph.qbra */, Mips::PRECEQU_PH_QBRA_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7384 { 7475 /* preceu.ph.qbl */, Mips::PRECEU_PH_QBL_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7386 { 7489 /* preceu.ph.qbla */, Mips::PRECEU_PH_QBLA_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7388 { 7504 /* preceu.ph.qbr */, Mips::PRECEU_PH_QBR_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7390 { 7518 /* preceu.ph.qbra */, Mips::PRECEU_PH_QBRA_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7398 { 7577 /* precrq.ph.w */, Mips::PRECRQ_PH_W_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7400 { 7589 /* precrq.qb.ph */, Mips::PRECRQ_QB_PH_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7402 { 7602 /* precrq_rs.ph.w */, Mips::PRECRQ_RS_PH_W_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7404 { 7617 /* precrqu_s.qb.ph */, Mips::PRECRQU_S_QB_PH_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7415 { 7658 /* raddu.w.qb */, Mips::RADDU_W_QB_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7417 { 7669 /* rddsp */, Mips::RDDSP_MM, Convert__GPR32AsmReg1_0__ConstantUImm7_01_1, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_ConstantUImm7_0 }, },
7441 { 7713 /* repl.ph */, Mips::REPL_PH_MM, Convert__GPR32AsmReg1_0__ConstantSImm10_01_1, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_ConstantSImm10_0 }, },
7443 { 7721 /* repl.qb */, Mips::REPL_QB_MM, Convert__GPR32AsmReg1_0__ConstantUImm8_01_1, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_ConstantUImm8_0 }, },
7445 { 7729 /* replv.ph */, Mips::REPLV_PH_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7447 { 7738 /* replv.qb */, Mips::REPLV_QB_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7614 { 8104 /* shilo */, Mips::SHILO_MM, Convert__ACC64DSPAsmReg1_0__ConstantSImm6_01_1__Tie0_1_1, AMFBS_InMicroMips_HasDSP, { MCK_ACC64DSPAsmReg, MCK_ConstantSImm6_0 }, },
7616 { 8110 /* shilov */, Mips::SHILOV_MM, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__Tie0_1_1, AMFBS_InMicroMips_HasDSP, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg }, },
7618 { 8117 /* shll.ph */, Mips::SHLL_PH_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm4_01_2, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm4_0 }, },
7620 { 8125 /* shll.qb */, Mips::SHLL_QB_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm3_01_2, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm3_0 }, },
7622 { 8133 /* shll_s.ph */, Mips::SHLL_S_PH_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm4_01_2, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm4_0 }, },
7624 { 8143 /* shll_s.w */, Mips::SHLL_S_W_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm5_01_2, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm5_0 }, },
7626 { 8152 /* shllv.ph */, Mips::SHLLV_PH_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7628 { 8161 /* shllv.qb */, Mips::SHLLV_QB_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7630 { 8170 /* shllv_s.ph */, Mips::SHLLV_S_PH_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7632 { 8181 /* shllv_s.w */, Mips::SHLLV_S_W_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7634 { 8191 /* shra.ph */, Mips::SHRA_PH_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm4_01_2, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm4_0 }, },
7638 { 8207 /* shra_r.ph */, Mips::SHRA_R_PH_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm4_01_2, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm4_0 }, },
7642 { 8227 /* shra_r.w */, Mips::SHRA_R_W_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm5_01_2, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm5_0 }, },
7644 { 8236 /* shrav.ph */, Mips::SHRAV_PH_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7648 { 8254 /* shrav_r.ph */, Mips::SHRAV_R_PH_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7652 { 8276 /* shrav_r.w */, Mips::SHRAV_R_W_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7656 { 8294 /* shrl.qb */, Mips::SHRL_QB_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm3_01_2, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm3_0 }, },
7660 { 8311 /* shrlv.qb */, Mips::SHRLV_QB_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7825 { 8847 /* subq.ph */, Mips::SUBQ_PH_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7827 { 8855 /* subq_s.ph */, Mips::SUBQ_S_PH_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7829 { 8865 /* subq_s.w */, Mips::SUBQ_S_W_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7866 { 9085 /* subu.qb */, Mips::SUBU_QB_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7872 { 9110 /* subu_s.qb */, Mips::SUBU_S_QB_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7893 { 9206 /* sw */, Mips::SWDSP_MM, Convert__GPR32AsmReg1_0__Mem2_1, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_Mem }, },
8036 { 9581 /* wrdsp */, Mips::WRDSP_MM, Convert__GPR32AsmReg1_0__ConstantUImm7_01_1, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_ConstantUImm7_0 }, },
8306 { 16 /* absq_s.ph */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP },
8310 { 36 /* absq_s.w */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP },
8349 { 146 /* addq.ph */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP },
8351 { 154 /* addq_s.ph */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP },
8353 { 164 /* addq_s.w */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP },
8375 { 319 /* addsc */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP },
8389 { 338 /* addu.qb */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP },
8395 { 363 /* addu_s.qb */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP },
8409 { 453 /* addwc */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP },
8686 { 1252 /* bitrev */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP },
9258 { 2425 /* cmp.eq.ph */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP },
9266 { 2453 /* cmp.le.ph */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP },
9274 { 2481 /* cmp.lt.ph */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP },
9356 { 2783 /* cmpgu.eq.qb */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP },
9358 { 2795 /* cmpgu.le.qb */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP },
9360 { 2807 /* cmpgu.lt.qb */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP },
9362 { 2824 /* cmpu.eq.qb */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP },
9364 { 2835 /* cmpu.le.qb */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP },
9366 { 2846 /* cmpu.lt.qb */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP },
9616 { 3574 /* dpaq_s.w.ph */, 1 /* 0 */, MCK_ACC64DSPAsmReg, AMFBS_InMicroMips_HasDSP },
9617 { 3574 /* dpaq_s.w.ph */, 6 /* 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP },
9620 { 3586 /* dpaq_sa.l.w */, 1 /* 0 */, MCK_ACC64DSPAsmReg, AMFBS_InMicroMips_HasDSP },
9621 { 3586 /* dpaq_sa.l.w */, 6 /* 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP },
9632 { 3625 /* dpau.h.qbl */, 1 /* 0 */, MCK_ACC64DSPAsmReg, AMFBS_InMicroMips_HasDSP },
9633 { 3625 /* dpau.h.qbl */, 6 /* 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP },
9636 { 3636 /* dpau.h.qbr */, 1 /* 0 */, MCK_ACC64DSPAsmReg, AMFBS_InMicroMips_HasDSP },
9637 { 3636 /* dpau.h.qbr */, 6 /* 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP },
9650 { 3671 /* dpsq_s.w.ph */, 1 /* 0 */, MCK_ACC64DSPAsmReg, AMFBS_InMicroMips_HasDSP },
9651 { 3671 /* dpsq_s.w.ph */, 6 /* 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP },
9654 { 3683 /* dpsq_sa.l.w */, 1 /* 0 */, MCK_ACC64DSPAsmReg, AMFBS_InMicroMips_HasDSP },
9655 { 3683 /* dpsq_sa.l.w */, 6 /* 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP },
9666 { 3722 /* dpsu.h.qbl */, 1 /* 0 */, MCK_ACC64DSPAsmReg, AMFBS_InMicroMips_HasDSP },
9667 { 3722 /* dpsu.h.qbl */, 6 /* 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP },
9670 { 3733 /* dpsu.h.qbr */, 1 /* 0 */, MCK_ACC64DSPAsmReg, AMFBS_InMicroMips_HasDSP },
9671 { 3733 /* dpsu.h.qbr */, 6 /* 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP },
9765 { 3982 /* extp */, 2 /* 1 */, MCK_ACC64DSPAsmReg, AMFBS_InMicroMips_HasDSP },
9766 { 3982 /* extp */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP },
9769 { 3987 /* extpdp */, 2 /* 1 */, MCK_ACC64DSPAsmReg, AMFBS_InMicroMips_HasDSP },
9770 { 3987 /* extpdp */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP },
9773 { 3994 /* extpdpv */, 2 /* 1 */, MCK_ACC64DSPAsmReg, AMFBS_InMicroMips_HasDSP },
9774 { 3994 /* extpdpv */, 5 /* 0, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP },
9777 { 4002 /* extpv */, 2 /* 1 */, MCK_ACC64DSPAsmReg, AMFBS_InMicroMips_HasDSP },
9778 { 4002 /* extpv */, 5 /* 0, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP },
9781 { 4008 /* extr.w */, 2 /* 1 */, MCK_ACC64DSPAsmReg, AMFBS_InMicroMips_HasDSP },
9782 { 4008 /* extr.w */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP },
9785 { 4015 /* extr_r.w */, 2 /* 1 */, MCK_ACC64DSPAsmReg, AMFBS_InMicroMips_HasDSP },
9786 { 4015 /* extr_r.w */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP },
9789 { 4024 /* extr_rs.w */, 2 /* 1 */, MCK_ACC64DSPAsmReg, AMFBS_InMicroMips_HasDSP },
9790 { 4024 /* extr_rs.w */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP },
9793 { 4034 /* extr_s.h */, 2 /* 1 */, MCK_ACC64DSPAsmReg, AMFBS_InMicroMips_HasDSP },
9794 { 4034 /* extr_s.h */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP },
9797 { 4043 /* extrv.w */, 2 /* 1 */, MCK_ACC64DSPAsmReg, AMFBS_InMicroMips_HasDSP },
9798 { 4043 /* extrv.w */, 5 /* 0, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP },
9801 { 4051 /* extrv_r.w */, 2 /* 1 */, MCK_ACC64DSPAsmReg, AMFBS_InMicroMips_HasDSP },
9802 { 4051 /* extrv_r.w */, 5 /* 0, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP },
9805 { 4061 /* extrv_rs.w */, 2 /* 1 */, MCK_ACC64DSPAsmReg, AMFBS_InMicroMips_HasDSP },
9806 { 4061 /* extrv_rs.w */, 5 /* 0, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP },
9809 { 4072 /* extrv_s.h */, 2 /* 1 */, MCK_ACC64DSPAsmReg, AMFBS_InMicroMips_HasDSP },
9810 { 4072 /* extrv_s.h */, 5 /* 0, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP },
9990 { 5261 /* insv */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP },
10082 { 5449 /* lbux */, 11 /* 0, 1, 3 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP },
10144 { 5557 /* lhx */, 11 /* 0, 1, 3 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP },
10192 { 5604 /* lw */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP },
10193 { 5604 /* lw */, 2 /* 1 */, MCK_Mem, AMFBS_InMicroMips_HasDSP },
10251 { 5684 /* lwx */, 11 /* 0, 1, 3 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP },
10260 { 5699 /* madd */, 1 /* 0 */, MCK_ACC64DSPAsmReg, AMFBS_InMicroMips_HasDSP },
10261 { 5699 /* madd */, 6 /* 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP },
10279 { 5772 /* maddu */, 1 /* 0 */, MCK_ACC64DSPAsmReg, AMFBS_InMicroMips_HasDSP },
10280 { 5772 /* maddu */, 6 /* 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP },
10287 { 5810 /* maq_s.w.phl */, 1 /* 0 */, MCK_ACC64DSPAsmReg, AMFBS_InMicroMips_HasDSP },
10288 { 5810 /* maq_s.w.phl */, 6 /* 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP },
10291 { 5822 /* maq_s.w.phr */, 1 /* 0 */, MCK_ACC64DSPAsmReg, AMFBS_InMicroMips_HasDSP },
10292 { 5822 /* maq_s.w.phr */, 6 /* 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP },
10295 { 5834 /* maq_sa.w.phl */, 1 /* 0 */, MCK_ACC64DSPAsmReg, AMFBS_InMicroMips_HasDSP },
10296 { 5834 /* maq_sa.w.phl */, 6 /* 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP },
10299 { 5847 /* maq_sa.w.phr */, 1 /* 0 */, MCK_ACC64DSPAsmReg, AMFBS_InMicroMips_HasDSP },
10300 { 5847 /* maq_sa.w.phr */, 6 /* 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP },
10385 { 6100 /* mfhi */, 2 /* 1 */, MCK_ACC64DSPAsmReg, AMFBS_InMicroMips_HasDSP },
10386 { 6100 /* mfhi */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP },
10392 { 6112 /* mflo */, 2 /* 1 */, MCK_ACC64DSPAsmReg, AMFBS_InMicroMips_HasDSP },
10393 { 6112 /* mflo */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP },
10455 { 6443 /* modsub */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP },
10534 { 6568 /* msub */, 1 /* 0 */, MCK_ACC64DSPAsmReg, AMFBS_InMicroMips_HasDSP },
10535 { 6568 /* msub */, 6 /* 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP },
10553 { 6641 /* msubu */, 1 /* 0 */, MCK_ACC64DSPAsmReg, AMFBS_InMicroMips_HasDSP },
10554 { 6641 /* msubu */, 6 /* 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP },
10617 { 6725 /* mthi */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP },
10618 { 6725 /* mthi */, 2 /* 1 */, MCK_HI32DSPAsmReg, AMFBS_InMicroMips_HasDSP },
10621 { 6730 /* mthlip */, 2 /* 1 */, MCK_ACC64DSPAsmReg, AMFBS_InMicroMips_HasDSP },
10622 { 6730 /* mthlip */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP },
10627 { 6737 /* mtlo */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP },
10628 { 6737 /* mtlo */, 2 /* 1 */, MCK_LO32DSPAsmReg, AMFBS_InMicroMips_HasDSP },
10684 { 6886 /* muleq_s.w.phl */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP },
10686 { 6900 /* muleq_s.w.phr */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP },
10688 { 6914 /* muleu_s.ph.qbl */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP },
10690 { 6929 /* muleu_s.ph.qbr */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP },
10696 { 6955 /* mulq_rs.ph */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP },
10710 { 7024 /* mulsaq_s.w.ph */, 1 /* 0 */, MCK_ACC64DSPAsmReg, AMFBS_InMicroMips_HasDSP },
10711 { 7024 /* mulsaq_s.w.ph */, 6 /* 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP },
10716 { 7038 /* mult */, 1 /* 0 */, MCK_ACC64DSPAsmReg, AMFBS_InMicroMips_HasDSP },
10717 { 7038 /* mult */, 6 /* 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP },
10722 { 7043 /* multu */, 1 /* 0 */, MCK_ACC64DSPAsmReg, AMFBS_InMicroMips_HasDSP },
10723 { 7043 /* multu */, 6 /* 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP },
10811 { 7245 /* packrl.ph */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP },
10825 { 7353 /* pick.ph */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP },
10827 { 7361 /* pick.qb */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP },
10833 { 7387 /* preceq.w.phl */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP },
10835 { 7400 /* preceq.w.phr */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP },
10837 { 7413 /* precequ.ph.qbl */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP },
10839 { 7428 /* precequ.ph.qbla */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP },
10841 { 7444 /* precequ.ph.qbr */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP },
10843 { 7459 /* precequ.ph.qbra */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP },
10845 { 7475 /* preceu.ph.qbl */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP },
10847 { 7489 /* preceu.ph.qbla */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP },
10849 { 7504 /* preceu.ph.qbr */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP },
10851 { 7518 /* preceu.ph.qbra */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP },
10859 { 7577 /* precrq.ph.w */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP },
10861 { 7589 /* precrq.qb.ph */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP },
10863 { 7602 /* precrq_rs.ph.w */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP },
10865 { 7617 /* precrqu_s.qb.ph */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP },
10876 { 7658 /* raddu.w.qb */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP },
10878 { 7669 /* rddsp */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP },
10909 { 7713 /* repl.ph */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP },
10911 { 7721 /* repl.qb */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP },
10913 { 7729 /* replv.ph */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP },
10915 { 7738 /* replv.qb */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP },
11117 { 8104 /* shilo */, 1 /* 0 */, MCK_ACC64DSPAsmReg, AMFBS_InMicroMips_HasDSP },
11119 { 8110 /* shilov */, 1 /* 0 */, MCK_ACC64DSPAsmReg, AMFBS_InMicroMips_HasDSP },
11120 { 8110 /* shilov */, 2 /* 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP },
11123 { 8117 /* shll.ph */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP },
11125 { 8125 /* shll.qb */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP },
11127 { 8133 /* shll_s.ph */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP },
11129 { 8143 /* shll_s.w */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP },
11131 { 8152 /* shllv.ph */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP },
11133 { 8161 /* shllv.qb */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP },
11135 { 8170 /* shllv_s.ph */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP },
11137 { 8181 /* shllv_s.w */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP },
11139 { 8191 /* shra.ph */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP },
11143 { 8207 /* shra_r.ph */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP },
11147 { 8227 /* shra_r.w */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP },
11149 { 8236 /* shrav.ph */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP },
11153 { 8254 /* shrav_r.ph */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP },
11157 { 8276 /* shrav_r.w */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP },
11161 { 8294 /* shrl.qb */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP },
11165 { 8311 /* shrlv.qb */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP },
11325 { 8847 /* subq.ph */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP },
11327 { 8855 /* subq_s.ph */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP },
11329 { 8865 /* subq_s.w */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP },
11367 { 9085 /* subu.qb */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP },
11373 { 9110 /* subu_s.qb */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP },
11401 { 9206 /* sw */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP },
11402 { 9206 /* sw */, 2 /* 1 */, MCK_Mem, AMFBS_InMicroMips_HasDSP },
11545 { 9581 /* wrdsp */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP },