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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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References
gen/lib/Target/Mips/MipsGenAsmMatcher.inc 5431 { 45 /* add */, Mips::ADDi_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__SImm32_Relaxed1_1, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_SImm32_Relaxed }, },
5436 { 45 /* add */, Mips::ADDi_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm32_Relaxed1_2, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_SImm32_Relaxed }, },
5467 { 112 /* addiur1sp */, Mips::ADDIUR1SP_MM, Convert__GPRMM16AsmReg1_0__UImm6Lsl21_1, AMFBS_InMicroMips, { MCK_GPRMM16AsmReg, MCK_UImm6Lsl2 }, },
5468 { 122 /* addiur2 */, Mips::ADDIUR2_MM, Convert__GPRMM16AsmReg1_0__GPRMM16AsmReg1_1__Imm1_2, AMFBS_InMicroMips, { MCK_GPRMM16AsmReg, MCK_GPRMM16AsmReg, MCK_Imm }, },
5469 { 130 /* addius5 */, Mips::ADDIUS5_MM, Convert__GPR32AsmReg1_0__Tie0_1_1__ConstantSImm4_01_1, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_ConstantSImm4_0 }, },
5470 { 138 /* addiusp */, Mips::ADDIUSP_MM, Convert__Imm1_0, AMFBS_InMicroMips, { MCK_Imm }, },
5503 { 325 /* addu */, Mips::ADDiu_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__SImm32_Relaxed1_1, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_SImm32_Relaxed }, },
5509 { 325 /* addu */, Mips::ADDiu_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm32_Relaxed1_2, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_SImm32_Relaxed }, },
5544 { 472 /* and */, Mips::ANDi_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__SImm32_Relaxed1_1, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_SImm32_Relaxed }, },
5551 { 472 /* and */, Mips::ANDi_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm32_Relaxed1_2, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_SImm32_Relaxed }, },
5596 { 732 /* b */, Mips::B_MM_Pseudo, Convert__JumpTarget1_0, AMFBS_InMicroMips, { MCK_JumpTarget }, },
5601 { 734 /* b16 */, Mips::B16_MM, Convert__JumpTarget1_0, AMFBS_InMicroMips, { MCK_JumpTarget }, },
5658 { 952 /* beqz */, Mips::BEQ_MM, Convert__GPR32AsmReg1_0__regZERO__JumpTarget1_1, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_JumpTarget }, },
5796 { 1493 /* bnez */, Mips::BNE_MM, Convert__GPR32AsmReg1_0__regZERO__JumpTarget1_1, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_JumpTarget }, },
5821 { 1592 /* break */, Mips::BREAK_MM, Convert__imm_95_0__imm_95_0, AMFBS_InMicroMips, { }, },
5824 { 1592 /* break */, Mips::BREAK_MM, Convert__ConstantUImm10_01_0__imm_95_0, AMFBS_InMicroMips, { MCK_ConstantUImm10_0 }, },
5827 { 1592 /* break */, Mips::BREAK_MM, Convert__ConstantUImm10_01_0__ConstantUImm10_01_1, AMFBS_InMicroMips, { MCK_ConstantUImm10_0, MCK_ConstantUImm10_0 }, },
6068 { 2068 /* cfc2 */, Mips::CFC2_MM, Convert__GPR32AsmReg1_0__COP2AsmReg1_1, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_COP2AsmReg }, },
6100 { 2250 /* clo */, Mips::CLO_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
6120 { 2390 /* clz */, Mips::CLZ_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
6229 { 2985 /* ctc2 */, Mips::CTC2_MM, Convert__COP2AsmReg1_1__GPR32AsmReg1_0, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_COP2AsmReg }, },
6302 { 3186 /* deret */, Mips::DERET_MM, Convert_NoOperands, AMFBS_InMicroMips, { }, },
6310 { 3209 /* di */, Mips::DI_MM, Convert__regZERO, AMFBS_InMicroMips, { }, },
6313 { 3209 /* di */, Mips::DI_MM, Convert__GPR32AsmReg1_0, AMFBS_InMicroMips, { MCK_GPR32AsmReg }, },
6510 { 3946 /* ehb */, Mips::EHB_MM, Convert_NoOperands, AMFBS_InMicroMips, { }, },
6513 { 3950 /* ei */, Mips::EI_MM, Convert__regZERO, AMFBS_InMicroMips, { }, },
6516 { 3950 /* ei */, Mips::EI_MM, Convert__GPR32AsmReg1_0, AMFBS_InMicroMips, { MCK_GPR32AsmReg }, },
6521 { 3957 /* eret */, Mips::ERET_MM, Convert_NoOperands, AMFBS_InMicroMips, { }, },
6794 { 5427 /* lb */, Mips::LB_MM, Convert__GPR32AsmReg1_0__MemOffsetSimm162_1, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_MemOffsetSimm16 }, },
6799 { 5434 /* lbu */, Mips::LBu_MM, Convert__GPR32AsmReg1_0__MemOffsetSimm162_1, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_MemOffsetSimm16 }, },
6801 { 5438 /* lbu16 */, Mips::LBU16_MM, Convert__GPRMM16AsmReg1_0__MicroMipsMem2_1, AMFBS_InMicroMips, { MCK_GPRMM16AsmReg, MCK_MicroMipsMem }, },
6830 { 5535 /* lh */, Mips::LH_MM, Convert__GPR32AsmReg1_0__MemOffsetSimmPtr2_1, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_MemOffsetSimmPtr }, },
6834 { 5542 /* lhu */, Mips::LHu_MM, Convert__GPR32AsmReg1_0__MemOffsetSimmPtr2_1, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_MemOffsetSimmPtr }, },
6835 { 5546 /* lhu16 */, Mips::LHU16_MM, Convert__GPRMM16AsmReg1_0__MicroMipsMem2_1, AMFBS_InMicroMips, { MCK_GPRMM16AsmReg, MCK_MicroMipsMem }, },
6870 { 5604 /* lw */, Mips::LWSP_MM, Convert__GPR32AsmReg1_0__MicroMipsMemSP2_1, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_MicroMipsMemSP }, },
6875 { 5604 /* lw */, Mips::LW_MM, Convert__GPR32AsmReg1_0__Mem2_1, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_Mem }, },
6876 { 5604 /* lw */, Mips::LWGP_MM, Convert__GPRMM16AsmReg1_0__MicroMipsMemGP2_1, AMFBS_InMicroMips, { MCK_GPRMM16AsmReg, MCK_MicroMipsMemGP }, },
6879 { 5607 /* lw16 */, Mips::LW16_MM, Convert__GPRMM16AsmReg1_0__MicroMipsMem2_1, AMFBS_InMicroMips, { MCK_GPRMM16AsmReg, MCK_MicroMipsMem }, },
6892 { 5640 /* lwm */, Mips::LWM_MM, Convert__RegList1_0__Mem2_1, AMFBS_InMicroMips, { MCK_RegList, MCK_Mem }, },
6895 { 5650 /* lwm32 */, Mips::LWM32_MM, Convert__RegList1_0__Mem2_1, AMFBS_InMicroMips, { MCK_RegList, MCK_Mem }, },
6896 { 5656 /* lwp */, Mips::LWP_MM, ConvertCustom_ConvertXWPOperands, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_MemOffsetSimm12 }, },
6910 { 5694 /* lwxs */, Mips::LWXS_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_3__GPR32AsmReg1_1, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK__40_, MCK_GPR32AsmReg, MCK__41_ }, },
7302 { 7191 /* nop */, Mips::SLL_MM, Convert__regZERO__regZERO__imm_95_0, AMFBS_InMicroMips, { }, },
7303 { 7191 /* nop */, Mips::MOVE16_MM, Convert__regZERO__regZERO, AMFBS_InMicroMips, { }, },
7328 { 7222 /* or */, Mips::ORi_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__SImm32_Relaxed1_1, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_SImm32_Relaxed }, },
7335 { 7222 /* or */, Mips::ORi_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm32_Relaxed1_2, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_SImm32_Relaxed }, },
7351 { 7255 /* pause */, Mips::PAUSE_MM, Convert_NoOperands, AMFBS_InMicroMips, { }, },
7462 { 7769 /* rotr */, Mips::ROTR_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__ConstantUImm5_01_1, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_ConstantUImm5_0 }, },
7463 { 7769 /* rotr */, Mips::ROTR_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__ConstantUImm5_01_1, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_ConstantUImm5_0 }, },
7465 { 7769 /* rotr */, Mips::ROTR_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm5_01_2, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm5_0 }, },
7467 { 7774 /* rotrv */, Mips::ROTRV_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7500 { 7908 /* sb */, Mips::SB_MM, Convert__GPR32AsmReg1_0__Mem2_1, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_Mem }, },
7521 { 7934 /* sdbbp */, Mips::SDBBP_MM, Convert__ConstantUImm10_01_0, AMFBS_InMicroMips, { MCK_ConstantUImm10_0 }, },
7541 { 7977 /* seb */, Mips::SEB_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0, AMFBS_InMicroMips, { MCK_GPR32AsmReg }, },
7543 { 7977 /* seb */, Mips::SEB_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7546 { 7981 /* seh */, Mips::SEH_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0, AMFBS_InMicroMips, { MCK_GPR32AsmReg }, },
7548 { 7981 /* seh */, Mips::SEH_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7588 { 8065 /* sgt */, Mips::SLT_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_0, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7592 { 8065 /* sgt */, Mips::SLT_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_2__GPR32AsmReg1_1, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7596 { 8069 /* sgtu */, Mips::SLTu_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_0, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7600 { 8069 /* sgtu */, Mips::SLTu_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_2__GPR32AsmReg1_1, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7605 { 8074 /* sh */, Mips::SH_MM, Convert__GPR32AsmReg1_0__Mem2_1, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_Mem }, },
7675 { 8379 /* sll */, Mips::SLLV_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7678 { 8379 /* sll */, Mips::SLL_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__ConstantUImm5_01_1, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_ConstantUImm5_0 }, },
7679 { 8379 /* sll */, Mips::SLL_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__ConstantUImm5_01_1, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_ConstantUImm5_0 }, },
7682 { 8379 /* sll */, Mips::SLLV_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7685 { 8379 /* sll */, Mips::SLL_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm5_01_2, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm5_0 }, },
7698 { 8441 /* sllv */, Mips::SLLV_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7701 { 8446 /* slt */, Mips::SLTi_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__SImm32_Relaxed1_1, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_SImm32_Relaxed }, },
7704 { 8446 /* slt */, Mips::SLT_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7706 { 8446 /* slt */, Mips::SLTi_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm32_Relaxed1_2, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_SImm32_Relaxed }, },
7710 { 8450 /* slti */, Mips::SLTi_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm161_2, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_SImm16 }, },
7714 { 8455 /* sltiu */, Mips::SLTiu_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm161_2, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_SImm16 }, },
7718 { 8461 /* sltu */, Mips::SLTiu_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__SImm32_Relaxed1_1, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_SImm32_Relaxed }, },
7721 { 8461 /* sltu */, Mips::SLTu_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7723 { 8461 /* sltu */, Mips::SLTiu_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm32_Relaxed1_2, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_SImm32_Relaxed }, },
7744 { 8557 /* sra */, Mips::SRAV_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7746 { 8557 /* sra */, Mips::SRA_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__ConstantUImm5_01_1, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_ConstantUImm5_0 }, },
7747 { 8557 /* sra */, Mips::SRA_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__ConstantUImm5_01_1, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_ConstantUImm5_0 }, },
7750 { 8557 /* sra */, Mips::SRAV_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7752 { 8557 /* sra */, Mips::SRA_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm5_01_2, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm5_0 }, },
7771 { 8673 /* srav */, Mips::SRAV_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7773 { 8678 /* srl */, Mips::SRLV_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7775 { 8678 /* srl */, Mips::SRL_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__ConstantUImm5_01_1, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_ConstantUImm5_0 }, },
7776 { 8678 /* srl */, Mips::SRL_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__ConstantUImm5_01_1, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_ConstantUImm5_0 }, },
7779 { 8678 /* srl */, Mips::SRLV_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7781 { 8678 /* srl */, Mips::SRL_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm5_01_2, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm5_0 }, },
7802 { 8800 /* srlv */, Mips::SRLV_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7805 { 8805 /* ssnop */, Mips::SSNOP_MM, Convert_NoOperands, AMFBS_InMicroMips, { }, },
7890 { 9206 /* sw */, Mips::SWSP_MM, Convert__GPR32AsmReg1_0__MicroMipsMemSP2_1, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_MicroMipsMemSP }, },
7895 { 9206 /* sw */, Mips::SW_MM, Convert__GPR32AsmReg1_0__Mem2_1, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_Mem }, },
7912 { 9242 /* swm */, Mips::SWM_MM, Convert__RegList1_0__Mem2_1, AMFBS_InMicroMips, { MCK_RegList, MCK_Mem }, },
7915 { 9252 /* swm32 */, Mips::SWM32_MM, Convert__RegList1_0__Mem2_1, AMFBS_InMicroMips, { MCK_RegList, MCK_Mem }, },
7916 { 9258 /* swp */, Mips::SWP_MM, ConvertCustom_ConvertXWPOperands, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_MemOffsetSimm12 }, },
7926 { 9282 /* sync */, Mips::SYNC_MM, Convert__imm_95_0, AMFBS_InMicroMips, { }, },
7929 { 9282 /* sync */, Mips::SYNC_MM, Convert__ConstantUImm5_01_0, AMFBS_InMicroMips, { MCK_ConstantUImm5_0 }, },
7938 { 9323 /* syscall */, Mips::SYSCALL_MM, Convert__imm_95_0, AMFBS_InMicroMips, { }, },
7939 { 9323 /* syscall */, Mips::SYSCALL_MM, Convert__ConstantUImm10_01_0, AMFBS_InMicroMips, { MCK_ConstantUImm10_0 }, },
7942 { 9331 /* teq */, Mips::TEQ_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__imm_95_0, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7943 { 9331 /* teq */, Mips::TEQ_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm4_01_2, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm4_0 }, },
7948 { 9340 /* tge */, Mips::TGE_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__imm_95_0, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7949 { 9340 /* tge */, Mips::TGE_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm4_01_2, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm4_0 }, },
7956 { 9355 /* tgeu */, Mips::TGEU_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__imm_95_0, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7957 { 9355 /* tgeu */, Mips::TGEU_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm4_01_2, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm4_0 }, },
7976 { 9418 /* tlbp */, Mips::TLBP_MM, Convert_NoOperands, AMFBS_InMicroMips, { }, },
7978 { 9423 /* tlbr */, Mips::TLBR_MM, Convert_NoOperands, AMFBS_InMicroMips, { }, },
7980 { 9428 /* tlbwi */, Mips::TLBWI_MM, Convert_NoOperands, AMFBS_InMicroMips, { }, },
7982 { 9434 /* tlbwr */, Mips::TLBWR_MM, Convert_NoOperands, AMFBS_InMicroMips, { }, },
7984 { 9440 /* tlt */, Mips::TLT_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__imm_95_0, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7985 { 9440 /* tlt */, Mips::TLT_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm4_01_2, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm4_0 }, },
7992 { 9455 /* tltu */, Mips::TLTU_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__imm_95_0, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7993 { 9455 /* tltu */, Mips::TLTU_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm4_01_2, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm4_0 }, },
7996 { 9460 /* tne */, Mips::TNE_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__imm_95_0, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7997 { 9460 /* tne */, Mips::TNE_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm4_01_2, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm4_0 }, },
8031 { 9576 /* wait */, Mips::WAIT_MM, Convert__imm_95_0, AMFBS_InMicroMips, { }, },
8033 { 9576 /* wait */, Mips::WAIT_MM, Convert__ConstantUImm10_01_0, AMFBS_InMicroMips, { MCK_ConstantUImm10_0 }, },
8041 { 9594 /* wsbh */, Mips::WSBH_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
8048 { 9599 /* xor */, Mips::XORi_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__SImm32_Relaxed1_1, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_SImm32_Relaxed }, },
8055 { 9599 /* xor */, Mips::XORi_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm32_Relaxed1_2, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_SImm32_Relaxed }, },
8316 { 45 /* add */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips },
8321 { 45 /* add */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips },
8346 { 112 /* addiur1sp */, 1 /* 0 */, MCK_GPRMM16AsmReg, AMFBS_InMicroMips },
8347 { 122 /* addiur2 */, 3 /* 0, 1 */, MCK_GPRMM16AsmReg, AMFBS_InMicroMips },
8348 { 130 /* addius5 */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips },
8381 { 325 /* addu */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips },
8386 { 325 /* addu */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips },
8420 { 472 /* and */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips },
8427 { 472 /* and */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips },
8472 { 732 /* b */, 1 /* 0 */, MCK_JumpTarget, AMFBS_InMicroMips },
8477 { 734 /* b16 */, 1 /* 0 */, MCK_JumpTarget, AMFBS_InMicroMips },
8563 { 952 /* beqz */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips },
8564 { 952 /* beqz */, 2 /* 1 */, MCK_JumpTarget, AMFBS_InMicroMips },
8805 { 1493 /* bnez */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips },
8806 { 1493 /* bnez */, 2 /* 1 */, MCK_JumpTarget, AMFBS_InMicroMips },
9192 { 2068 /* cfc2 */, 2 /* 1 */, MCK_COP2AsmReg, AMFBS_InMicroMips },
9193 { 2068 /* cfc2 */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips },
9227 { 2250 /* clo */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips },
9247 { 2390 /* clz */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips },
9394 { 2985 /* ctc2 */, 2 /* 1 */, MCK_COP2AsmReg, AMFBS_InMicroMips },
9395 { 2985 /* ctc2 */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips },
9499 { 3209 /* di */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips },
9757 { 3950 /* ei */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips },
10062 { 5427 /* lb */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips },
10063 { 5427 /* lb */, 2 /* 1 */, MCK_MemOffsetSimm16, AMFBS_InMicroMips },
10072 { 5434 /* lbu */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips },
10073 { 5434 /* lbu */, 2 /* 1 */, MCK_MemOffsetSimm16, AMFBS_InMicroMips },
10076 { 5438 /* lbu16 */, 1 /* 0 */, MCK_GPRMM16AsmReg, AMFBS_InMicroMips },
10077 { 5438 /* lbu16 */, 2 /* 1 */, MCK_MicroMipsMem, AMFBS_InMicroMips },
10128 { 5535 /* lh */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips },
10129 { 5535 /* lh */, 2 /* 1 */, MCK_MemOffsetSimmPtr, AMFBS_InMicroMips },
10136 { 5542 /* lhu */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips },
10137 { 5542 /* lhu */, 2 /* 1 */, MCK_MemOffsetSimmPtr, AMFBS_InMicroMips },
10138 { 5546 /* lhu16 */, 1 /* 0 */, MCK_GPRMM16AsmReg, AMFBS_InMicroMips },
10139 { 5546 /* lhu16 */, 2 /* 1 */, MCK_MicroMipsMem, AMFBS_InMicroMips },
10186 { 5604 /* lw */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips },
10187 { 5604 /* lw */, 2 /* 1 */, MCK_MicroMipsMemSP, AMFBS_InMicroMips },
10196 { 5604 /* lw */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips },
10197 { 5604 /* lw */, 2 /* 1 */, MCK_Mem, AMFBS_InMicroMips },
10198 { 5604 /* lw */, 1 /* 0 */, MCK_GPRMM16AsmReg, AMFBS_InMicroMips },
10199 { 5604 /* lw */, 2 /* 1 */, MCK_MicroMipsMemGP, AMFBS_InMicroMips },
10200 { 5607 /* lw16 */, 1 /* 0 */, MCK_GPRMM16AsmReg, AMFBS_InMicroMips },
10201 { 5607 /* lw16 */, 2 /* 1 */, MCK_MicroMipsMem, AMFBS_InMicroMips },
10226 { 5640 /* lwm */, 2 /* 1 */, MCK_Mem, AMFBS_InMicroMips },
10227 { 5640 /* lwm */, 1 /* 0 */, MCK_RegList, AMFBS_InMicroMips },
10232 { 5650 /* lwm32 */, 2 /* 1 */, MCK_Mem, AMFBS_InMicroMips },
10233 { 5650 /* lwm32 */, 1 /* 0 */, MCK_RegList, AMFBS_InMicroMips },
10234 { 5656 /* lwp */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips },
10235 { 5656 /* lwp */, 2 /* 1 */, MCK_MemOffsetSimm12, AMFBS_InMicroMips },
10257 { 5694 /* lwxs */, 11 /* 0, 1, 3 */, MCK_GPR32AsmReg, AMFBS_InMicroMips },
10792 { 7222 /* or */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips },
10799 { 7222 /* or */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips },
10930 { 7769 /* rotr */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips },
10931 { 7769 /* rotr */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips },
10933 { 7769 /* rotr */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips },
10935 { 7774 /* rotrv */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips },
10980 { 7908 /* sb */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips },
10981 { 7908 /* sb */, 2 /* 1 */, MCK_Mem, AMFBS_InMicroMips },
11039 { 7977 /* seb */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips },
11041 { 7977 /* seb */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips },
11043 { 7981 /* seh */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips },
11045 { 7981 /* seh */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips },
11085 { 8065 /* sgt */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips },
11089 { 8065 /* sgt */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips },
11093 { 8069 /* sgtu */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips },
11097 { 8069 /* sgtu */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips },
11104 { 8074 /* sh */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips },
11105 { 8074 /* sh */, 2 /* 1 */, MCK_Mem, AMFBS_InMicroMips },
11180 { 8379 /* sll */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips },
11183 { 8379 /* sll */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips },
11184 { 8379 /* sll */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips },
11186 { 8379 /* sll */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips },
11189 { 8379 /* sll */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips },
11201 { 8441 /* sllv */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips },
11203 { 8446 /* slt */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips },
11206 { 8446 /* slt */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips },
11208 { 8446 /* slt */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips },
11211 { 8450 /* slti */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips },
11213 { 8455 /* sltiu */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips },
11215 { 8461 /* sltu */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips },
11218 { 8461 /* sltu */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips },
11220 { 8461 /* sltu */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips },
11245 { 8557 /* sra */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips },
11247 { 8557 /* sra */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips },
11248 { 8557 /* sra */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips },
11250 { 8557 /* sra */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips },
11252 { 8557 /* sra */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips },
11270 { 8673 /* srav */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips },
11272 { 8678 /* srl */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips },
11274 { 8678 /* srl */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips },
11275 { 8678 /* srl */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips },
11277 { 8678 /* srl */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips },
11279 { 8678 /* srl */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips },
11299 { 8800 /* srlv */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips },
11395 { 9206 /* sw */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips },
11396 { 9206 /* sw */, 2 /* 1 */, MCK_MicroMipsMemSP, AMFBS_InMicroMips },
11405 { 9206 /* sw */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips },
11406 { 9206 /* sw */, 2 /* 1 */, MCK_Mem, AMFBS_InMicroMips },
11435 { 9242 /* swm */, 2 /* 1 */, MCK_Mem, AMFBS_InMicroMips },
11436 { 9242 /* swm */, 1 /* 0 */, MCK_RegList, AMFBS_InMicroMips },
11441 { 9252 /* swm32 */, 2 /* 1 */, MCK_Mem, AMFBS_InMicroMips },
11442 { 9252 /* swm32 */, 1 /* 0 */, MCK_RegList, AMFBS_InMicroMips },
11443 { 9258 /* swp */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips },
11444 { 9258 /* swp */, 2 /* 1 */, MCK_MemOffsetSimm12, AMFBS_InMicroMips },
11463 { 9331 /* teq */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips },
11464 { 9331 /* teq */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips },
11469 { 9340 /* tge */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips },
11470 { 9340 /* tge */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips },
11477 { 9355 /* tgeu */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips },
11478 { 9355 /* tgeu */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips },
11481 { 9440 /* tlt */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips },
11482 { 9440 /* tlt */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips },
11489 { 9455 /* tltu */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips },
11490 { 9455 /* tltu */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips },
11493 { 9460 /* tne */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips },
11494 { 9460 /* tne */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips },
11550 { 9594 /* wsbh */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips },
11556 { 9599 /* xor */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips },
11563 { 9599 /* xor */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips },