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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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References
gen/lib/Target/Mips/MipsGenAsmMatcher.inc 6070 { 2080 /* cftc1 */, Mips::CFTC1, Convert__GPR32AsmReg1_0__FGR32AsmReg1_1, AMFBS_HasMT, { MCK_GPR32AsmReg, MCK_FGR32AsmReg }, },
6231 { 2997 /* cttc1 */, Mips::CTTC1, Convert__FGR32AsmReg1_1__GPR32AsmReg1_0, AMFBS_HasMT, { MCK_GPR32AsmReg, MCK_FGR32AsmReg }, },
7011 { 6124 /* mftacx */, Mips::MFTACX, Convert__GPR32AsmReg1_0__ACC64DSPAsmReg1_1, AMFBS_HasMT, { MCK_GPR32AsmReg, MCK_ACC64DSPAsmReg }, },
7013 { 6131 /* mftc0 */, Mips::MFTC0, Convert__GPR32AsmReg1_0__COP0AsmReg1_1__ConstantUImm3_01_2, AMFBS_HasMT, { MCK_GPR32AsmReg, MCK_COP0AsmReg, MCK_ConstantUImm3_0 }, },
7014 { 6137 /* mftc1 */, Mips::MFTC1, Convert__GPR32AsmReg1_0__FGR32AsmReg1_1, AMFBS_HasMT, { MCK_GPR32AsmReg, MCK_FGR32AsmReg }, },
7015 { 6143 /* mftdsp */, Mips::MFTDSP, Convert__GPR32AsmReg1_0, AMFBS_HasMT, { MCK_GPR32AsmReg }, },
7016 { 6150 /* mftgpr */, Mips::MFTGPR, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__imm_95_0, AMFBS_HasMT, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7017 { 6157 /* mfthc1 */, Mips::MFTHC1, Convert__GPR32AsmReg1_0__FGR32AsmReg1_1, AMFBS_HasMT, { MCK_GPR32AsmReg, MCK_FGR32AsmReg }, },
7019 { 6164 /* mfthi */, Mips::MFTHI, Convert__GPR32AsmReg1_0__ACC64DSPAsmReg1_1, AMFBS_HasMT, { MCK_GPR32AsmReg, MCK_ACC64DSPAsmReg }, },
7021 { 6170 /* mftlo */, Mips::MFTLO, Convert__GPR32AsmReg1_0__ACC64DSPAsmReg1_1, AMFBS_HasMT, { MCK_GPR32AsmReg, MCK_ACC64DSPAsmReg }, },
7181 { 6772 /* mttacx */, Mips::MTTACX, Convert__ACC64DSPAsmReg1_1__GPR32AsmReg1_0, AMFBS_HasMT, { MCK_GPR32AsmReg, MCK_ACC64DSPAsmReg }, },
7183 { 6779 /* mttc0 */, Mips::MTTC0, Convert__COP0AsmReg1_1__GPR32AsmReg1_0__ConstantUImm3_01_2, AMFBS_HasMT, { MCK_GPR32AsmReg, MCK_COP0AsmReg, MCK_ConstantUImm3_0 }, },
7184 { 6785 /* mttc1 */, Mips::MTTC1, Convert__FGR32AsmReg1_1__GPR32AsmReg1_0, AMFBS_HasMT, { MCK_GPR32AsmReg, MCK_FGR32AsmReg }, },
7185 { 6791 /* mttdsp */, Mips::MTTDSP, Convert__GPR32AsmReg1_0, AMFBS_HasMT, { MCK_GPR32AsmReg }, },
7186 { 6798 /* mttgpr */, Mips::MTTGPR, Convert__GPR32AsmReg1_1__GPR32AsmReg1_0, AMFBS_HasMT, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7187 { 6805 /* mtthc1 */, Mips::MTTHC1, Convert__FGR32AsmReg1_1__GPR32AsmReg1_0, AMFBS_HasMT, { MCK_GPR32AsmReg, MCK_FGR32AsmReg }, },
7189 { 6812 /* mtthi */, Mips::MTTHI, Convert__ACC64DSPAsmReg1_1__GPR32AsmReg1_0, AMFBS_HasMT, { MCK_GPR32AsmReg, MCK_ACC64DSPAsmReg }, },
7191 { 6818 /* mttlo */, Mips::MTTLO, Convert__ACC64DSPAsmReg1_1__GPR32AsmReg1_0, AMFBS_HasMT, { MCK_GPR32AsmReg, MCK_ACC64DSPAsmReg }, },
9196 { 2080 /* cftc1 */, 2 /* 1 */, MCK_FGR32AsmReg, AMFBS_HasMT },
9197 { 2080 /* cftc1 */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasMT },
9398 { 2997 /* cttc1 */, 2 /* 1 */, MCK_FGR32AsmReg, AMFBS_HasMT },
9399 { 2997 /* cttc1 */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasMT },
10398 { 6124 /* mftacx */, 2 /* 1 */, MCK_ACC64DSPAsmReg, AMFBS_HasMT },
10399 { 6124 /* mftacx */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasMT },
10402 { 6131 /* mftc0 */, 2 /* 1 */, MCK_COP0AsmReg, AMFBS_HasMT },
10403 { 6131 /* mftc0 */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasMT },
10404 { 6137 /* mftc1 */, 2 /* 1 */, MCK_FGR32AsmReg, AMFBS_HasMT },
10405 { 6137 /* mftc1 */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasMT },
10406 { 6143 /* mftdsp */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasMT },
10407 { 6150 /* mftgpr */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasMT },
10408 { 6157 /* mfthc1 */, 2 /* 1 */, MCK_FGR32AsmReg, AMFBS_HasMT },
10409 { 6157 /* mfthc1 */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasMT },
10411 { 6164 /* mfthi */, 2 /* 1 */, MCK_ACC64DSPAsmReg, AMFBS_HasMT },
10412 { 6164 /* mfthi */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasMT },
10414 { 6170 /* mftlo */, 2 /* 1 */, MCK_ACC64DSPAsmReg, AMFBS_HasMT },
10415 { 6170 /* mftlo */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasMT },
10638 { 6772 /* mttacx */, 2 /* 1 */, MCK_ACC64DSPAsmReg, AMFBS_HasMT },
10639 { 6772 /* mttacx */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasMT },
10642 { 6779 /* mttc0 */, 2 /* 1 */, MCK_COP0AsmReg, AMFBS_HasMT },
10643 { 6779 /* mttc0 */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasMT },
10644 { 6785 /* mttc1 */, 2 /* 1 */, MCK_FGR32AsmReg, AMFBS_HasMT },
10645 { 6785 /* mttc1 */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasMT },
10646 { 6791 /* mttdsp */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasMT },
10647 { 6798 /* mttgpr */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasMT },
10648 { 6805 /* mtthc1 */, 2 /* 1 */, MCK_FGR32AsmReg, AMFBS_HasMT },
10649 { 6805 /* mtthc1 */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasMT },
10651 { 6812 /* mtthi */, 2 /* 1 */, MCK_ACC64DSPAsmReg, AMFBS_HasMT },
10652 { 6812 /* mtthi */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasMT },
10654 { 6818 /* mttlo */, 2 /* 1 */, MCK_ACC64DSPAsmReg, AMFBS_HasMT },
10655 { 6818 /* mttlo */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasMT },