|
|
reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
|
References
gen/lib/Target/Mips/MipsGenAsmMatcher.inc 5422 { 16 /* absq_s.ph */, Mips::ABSQ_S_PH, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
5426 { 36 /* absq_s.w */, Mips::ABSQ_S_W, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
5472 { 146 /* addq.ph */, Mips::ADDQ_PH, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
5474 { 154 /* addq_s.ph */, Mips::ADDQ_S_PH, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
5476 { 164 /* addq_s.w */, Mips::ADDQ_S_W, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
5498 { 319 /* addsc */, Mips::ADDSC, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
5513 { 338 /* addu.qb */, Mips::ADDU_QB, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
5519 { 363 /* addu_s.qb */, Mips::ADDU_S_QB, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
5533 { 453 /* addwc */, Mips::ADDWC, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
5729 { 1252 /* bitrev */, Mips::BITREV, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
6129 { 2425 /* cmp.eq.ph */, Mips::CMP_EQ_PH, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
6135 { 2453 /* cmp.le.ph */, Mips::CMP_LE_PH, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
6141 { 2481 /* cmp.lt.ph */, Mips::CMP_LT_PH, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
6199 { 2783 /* cmpgu.eq.qb */, Mips::CMPGU_EQ_QB, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
6201 { 2795 /* cmpgu.le.qb */, Mips::CMPGU_LE_QB, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
6203 { 2807 /* cmpgu.lt.qb */, Mips::CMPGU_LT_QB, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
6207 { 2824 /* cmpu.eq.qb */, Mips::CMPU_EQ_QB, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
6209 { 2835 /* cmpu.le.qb */, Mips::CMPU_LE_QB, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
6211 { 2846 /* cmpu.lt.qb */, Mips::CMPU_LT_QB, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
6412 { 3574 /* dpaq_s.w.ph */, Mips::DPAQ_S_W_PH, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, AMFBS_HasDSP, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
6414 { 3586 /* dpaq_sa.l.w */, Mips::DPAQ_SA_L_W, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, AMFBS_HasDSP, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
6420 { 3625 /* dpau.h.qbl */, Mips::DPAU_H_QBL, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, AMFBS_HasDSP, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
6422 { 3636 /* dpau.h.qbr */, Mips::DPAU_H_QBR, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, AMFBS_HasDSP, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
6430 { 3671 /* dpsq_s.w.ph */, Mips::DPSQ_S_W_PH, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, AMFBS_HasDSP, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
6432 { 3683 /* dpsq_sa.l.w */, Mips::DPSQ_SA_L_W, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, AMFBS_HasDSP, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
6438 { 3722 /* dpsu.h.qbl */, Mips::DPSU_H_QBL, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, AMFBS_HasDSP, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
6440 { 3733 /* dpsu.h.qbr */, Mips::DPSU_H_QBR, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, AMFBS_HasDSP, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
6534 { 3982 /* extp */, Mips::EXTP, Convert__GPR32AsmReg1_0__ACC64DSPAsmReg1_1__ConstantUImm5_01_2, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_ACC64DSPAsmReg, MCK_ConstantUImm5_0 }, },
6536 { 3987 /* extpdp */, Mips::EXTPDP, Convert__GPR32AsmReg1_0__ACC64DSPAsmReg1_1__ConstantUImm5_01_2, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_ACC64DSPAsmReg, MCK_ConstantUImm5_0 }, },
6538 { 3994 /* extpdpv */, Mips::EXTPDPV, Convert__GPR32AsmReg1_0__ACC64DSPAsmReg1_1__GPR32AsmReg1_2, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg }, },
6540 { 4002 /* extpv */, Mips::EXTPV, Convert__GPR32AsmReg1_0__ACC64DSPAsmReg1_1__GPR32AsmReg1_2, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg }, },
6542 { 4008 /* extr.w */, Mips::EXTR_W, Convert__GPR32AsmReg1_0__ACC64DSPAsmReg1_1__ConstantUImm5_01_2, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_ACC64DSPAsmReg, MCK_ConstantUImm5_0 }, },
6544 { 4015 /* extr_r.w */, Mips::EXTR_R_W, Convert__GPR32AsmReg1_0__ACC64DSPAsmReg1_1__ConstantUImm5_01_2, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_ACC64DSPAsmReg, MCK_ConstantUImm5_0 }, },
6546 { 4024 /* extr_rs.w */, Mips::EXTR_RS_W, Convert__GPR32AsmReg1_0__ACC64DSPAsmReg1_1__ConstantUImm5_01_2, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_ACC64DSPAsmReg, MCK_ConstantUImm5_0 }, },
6548 { 4034 /* extr_s.h */, Mips::EXTR_S_H, Convert__GPR32AsmReg1_0__ACC64DSPAsmReg1_1__ConstantUImm5_01_2, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_ACC64DSPAsmReg, MCK_ConstantUImm5_0 }, },
6550 { 4043 /* extrv.w */, Mips::EXTRV_W, Convert__GPR32AsmReg1_0__ACC64DSPAsmReg1_1__GPR32AsmReg1_2, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg }, },
6552 { 4051 /* extrv_r.w */, Mips::EXTRV_R_W, Convert__GPR32AsmReg1_0__ACC64DSPAsmReg1_1__GPR32AsmReg1_2, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg }, },
6554 { 4061 /* extrv_rs.w */, Mips::EXTRV_RS_W, Convert__GPR32AsmReg1_0__ACC64DSPAsmReg1_1__GPR32AsmReg1_2, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg }, },
6556 { 4072 /* extrv_s.h */, Mips::EXTRV_S_H, Convert__GPR32AsmReg1_0__ACC64DSPAsmReg1_1__GPR32AsmReg1_2, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg }, },
6725 { 5261 /* insv */, Mips::INSV, Convert__GPR32AsmReg1_0__Tie0_1_1__GPR32AsmReg1_1, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
6805 { 5449 /* lbux */, Mips::LBUX, Convert__GPR32AsmReg1_0__GPR32AsmReg1_3__GPR32AsmReg1_1, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK__40_, MCK_GPR32AsmReg, MCK__41_ }, },
6839 { 5557 /* lhx */, Mips::LHX, Convert__GPR32AsmReg1_0__GPR32AsmReg1_3__GPR32AsmReg1_1, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK__40_, MCK_GPR32AsmReg, MCK__41_ }, },
6907 { 5684 /* lwx */, Mips::LWX, Convert__GPR32AsmReg1_0__GPR32AsmReg1_3__GPR32AsmReg1_1, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK__40_, MCK_GPR32AsmReg, MCK__41_ }, },
6914 { 5699 /* madd */, Mips::MADD_DSP, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, AMFBS_HasDSP, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
6931 { 5772 /* maddu */, Mips::MADDU_DSP, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, AMFBS_HasDSP, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
6937 { 5810 /* maq_s.w.phl */, Mips::MAQ_S_W_PHL, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, AMFBS_HasDSP, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
6939 { 5822 /* maq_s.w.phr */, Mips::MAQ_S_W_PHR, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, AMFBS_HasDSP, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
6941 { 5834 /* maq_sa.w.phl */, Mips::MAQ_SA_W_PHL, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, AMFBS_HasDSP, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
6943 { 5847 /* maq_sa.w.phr */, Mips::MAQ_SA_W_PHR, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, AMFBS_HasDSP, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7002 { 6100 /* mfhi */, Mips::MFHI_DSP, Convert__GPR32AsmReg1_0__ACC64DSPAsmReg1_1, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_ACC64DSPAsmReg }, },
7008 { 6112 /* mflo */, Mips::MFLO_DSP, Convert__GPR32AsmReg1_0__ACC64DSPAsmReg1_1, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_ACC64DSPAsmReg }, },
7062 { 6443 /* modsub */, Mips::MODSUB, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7115 { 6568 /* msub */, Mips::MSUB_DSP, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, AMFBS_HasDSP, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7132 { 6641 /* msubu */, Mips::MSUBU_DSP, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, AMFBS_HasDSP, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7167 { 6725 /* mthi */, Mips::MTHI_DSP, Convert__HI32DSPAsmReg1_1__GPR32AsmReg1_0, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_HI32DSPAsmReg }, },
7169 { 6730 /* mthlip */, Mips::MTHLIP, Convert__ACC64DSPAsmReg1_1__GPR32AsmReg1_0__Tie0_1_1, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_ACC64DSPAsmReg }, },
7173 { 6737 /* mtlo */, Mips::MTLO_DSP, Convert__LO32DSPAsmReg1_1__GPR32AsmReg1_0, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_LO32DSPAsmReg }, },
7221 { 6886 /* muleq_s.w.phl */, Mips::MULEQ_S_W_PHL, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7223 { 6900 /* muleq_s.w.phr */, Mips::MULEQ_S_W_PHR, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7225 { 6914 /* muleu_s.ph.qbl */, Mips::MULEU_S_PH_QBL, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7227 { 6929 /* muleu_s.ph.qbr */, Mips::MULEU_S_PH_QBR, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7233 { 6955 /* mulq_rs.ph */, Mips::MULQ_RS_PH, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7245 { 7024 /* mulsaq_s.w.ph */, Mips::MULSAQ_S_W_PH, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, AMFBS_HasDSP, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7249 { 7038 /* mult */, Mips::MULT_DSP, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasDSP, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7253 { 7043 /* multu */, Mips::MULTU_DSP, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasDSP, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7348 { 7245 /* packrl.ph */, Mips::PACKRL_PH, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7365 { 7353 /* pick.ph */, Mips::PICK_PH, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7367 { 7361 /* pick.qb */, Mips::PICK_QB, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7373 { 7387 /* preceq.w.phl */, Mips::PRECEQ_W_PHL, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7375 { 7400 /* preceq.w.phr */, Mips::PRECEQ_W_PHR, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7377 { 7413 /* precequ.ph.qbl */, Mips::PRECEQU_PH_QBL, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7379 { 7428 /* precequ.ph.qbla */, Mips::PRECEQU_PH_QBLA, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7381 { 7444 /* precequ.ph.qbr */, Mips::PRECEQU_PH_QBR, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7383 { 7459 /* precequ.ph.qbra */, Mips::PRECEQU_PH_QBRA, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7385 { 7475 /* preceu.ph.qbl */, Mips::PRECEU_PH_QBL, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7387 { 7489 /* preceu.ph.qbla */, Mips::PRECEU_PH_QBLA, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7389 { 7504 /* preceu.ph.qbr */, Mips::PRECEU_PH_QBR, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7391 { 7518 /* preceu.ph.qbra */, Mips::PRECEU_PH_QBRA, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7399 { 7577 /* precrq.ph.w */, Mips::PRECRQ_PH_W, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7401 { 7589 /* precrq.qb.ph */, Mips::PRECRQ_QB_PH, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7403 { 7602 /* precrq_rs.ph.w */, Mips::PRECRQ_RS_PH_W, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7405 { 7617 /* precrqu_s.qb.ph */, Mips::PRECRQU_S_QB_PH, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7416 { 7658 /* raddu.w.qb */, Mips::RADDU_W_QB, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7418 { 7669 /* rddsp */, Mips::RDDSP, Convert__GPR32AsmReg1_0__ConstantUImm10_01_1, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_ConstantUImm10_0 }, },
7442 { 7713 /* repl.ph */, Mips::REPL_PH, Convert__GPR32AsmReg1_0__ConstantSImm10_01_1, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_ConstantSImm10_0 }, },
7444 { 7721 /* repl.qb */, Mips::REPL_QB, Convert__GPR32AsmReg1_0__ConstantUImm8_01_1, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_ConstantUImm8_0 }, },
7446 { 7729 /* replv.ph */, Mips::REPLV_PH, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7448 { 7738 /* replv.qb */, Mips::REPLV_QB, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7615 { 8104 /* shilo */, Mips::SHILO, Convert__ACC64DSPAsmReg1_0__ConstantSImm6_01_1__Tie0_1_1, AMFBS_HasDSP, { MCK_ACC64DSPAsmReg, MCK_ConstantSImm6_0 }, },
7617 { 8110 /* shilov */, Mips::SHILOV, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__Tie0_1_1, AMFBS_HasDSP, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg }, },
7619 { 8117 /* shll.ph */, Mips::SHLL_PH, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm4_01_2, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm4_0 }, },
7621 { 8125 /* shll.qb */, Mips::SHLL_QB, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm3_01_2, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm3_0 }, },
7623 { 8133 /* shll_s.ph */, Mips::SHLL_S_PH, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm4_01_2, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm4_0 }, },
7625 { 8143 /* shll_s.w */, Mips::SHLL_S_W, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm5_01_2, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm5_0 }, },
7627 { 8152 /* shllv.ph */, Mips::SHLLV_PH, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7629 { 8161 /* shllv.qb */, Mips::SHLLV_QB, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7631 { 8170 /* shllv_s.ph */, Mips::SHLLV_S_PH, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7633 { 8181 /* shllv_s.w */, Mips::SHLLV_S_W, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7635 { 8191 /* shra.ph */, Mips::SHRA_PH, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm4_01_2, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm4_0 }, },
7639 { 8207 /* shra_r.ph */, Mips::SHRA_R_PH, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm4_01_2, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm4_0 }, },
7643 { 8227 /* shra_r.w */, Mips::SHRA_R_W, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm5_01_2, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm5_0 }, },
7645 { 8236 /* shrav.ph */, Mips::SHRAV_PH, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7649 { 8254 /* shrav_r.ph */, Mips::SHRAV_R_PH, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7653 { 8276 /* shrav_r.w */, Mips::SHRAV_R_W, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7657 { 8294 /* shrl.qb */, Mips::SHRL_QB, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm3_01_2, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm3_0 }, },
7661 { 8311 /* shrlv.qb */, Mips::SHRLV_QB, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7826 { 8847 /* subq.ph */, Mips::SUBQ_PH, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7828 { 8855 /* subq_s.ph */, Mips::SUBQ_S_PH, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7830 { 8865 /* subq_s.w */, Mips::SUBQ_S_W, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7867 { 9085 /* subu.qb */, Mips::SUBU_QB, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7873 { 9110 /* subu_s.qb */, Mips::SUBU_S_QB, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
8307 { 16 /* absq_s.ph */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasDSP },
8311 { 36 /* absq_s.w */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasDSP },
8350 { 146 /* addq.ph */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSP },
8352 { 154 /* addq_s.ph */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSP },
8354 { 164 /* addq_s.w */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSP },
8376 { 319 /* addsc */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSP },
8390 { 338 /* addu.qb */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSP },
8396 { 363 /* addu_s.qb */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSP },
8410 { 453 /* addwc */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSP },
8687 { 1252 /* bitrev */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasDSP },
9259 { 2425 /* cmp.eq.ph */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasDSP },
9267 { 2453 /* cmp.le.ph */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasDSP },
9275 { 2481 /* cmp.lt.ph */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasDSP },
9357 { 2783 /* cmpgu.eq.qb */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSP },
9359 { 2795 /* cmpgu.le.qb */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSP },
9361 { 2807 /* cmpgu.lt.qb */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSP },
9363 { 2824 /* cmpu.eq.qb */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasDSP },
9365 { 2835 /* cmpu.le.qb */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasDSP },
9367 { 2846 /* cmpu.lt.qb */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasDSP },
9618 { 3574 /* dpaq_s.w.ph */, 1 /* 0 */, MCK_ACC64DSPAsmReg, AMFBS_HasDSP },
9619 { 3574 /* dpaq_s.w.ph */, 6 /* 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSP },
9622 { 3586 /* dpaq_sa.l.w */, 1 /* 0 */, MCK_ACC64DSPAsmReg, AMFBS_HasDSP },
9623 { 3586 /* dpaq_sa.l.w */, 6 /* 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSP },
9634 { 3625 /* dpau.h.qbl */, 1 /* 0 */, MCK_ACC64DSPAsmReg, AMFBS_HasDSP },
9635 { 3625 /* dpau.h.qbl */, 6 /* 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSP },
9638 { 3636 /* dpau.h.qbr */, 1 /* 0 */, MCK_ACC64DSPAsmReg, AMFBS_HasDSP },
9639 { 3636 /* dpau.h.qbr */, 6 /* 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSP },
9652 { 3671 /* dpsq_s.w.ph */, 1 /* 0 */, MCK_ACC64DSPAsmReg, AMFBS_HasDSP },
9653 { 3671 /* dpsq_s.w.ph */, 6 /* 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSP },
9656 { 3683 /* dpsq_sa.l.w */, 1 /* 0 */, MCK_ACC64DSPAsmReg, AMFBS_HasDSP },
9657 { 3683 /* dpsq_sa.l.w */, 6 /* 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSP },
9668 { 3722 /* dpsu.h.qbl */, 1 /* 0 */, MCK_ACC64DSPAsmReg, AMFBS_HasDSP },
9669 { 3722 /* dpsu.h.qbl */, 6 /* 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSP },
9672 { 3733 /* dpsu.h.qbr */, 1 /* 0 */, MCK_ACC64DSPAsmReg, AMFBS_HasDSP },
9673 { 3733 /* dpsu.h.qbr */, 6 /* 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSP },
9767 { 3982 /* extp */, 2 /* 1 */, MCK_ACC64DSPAsmReg, AMFBS_HasDSP },
9768 { 3982 /* extp */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasDSP },
9771 { 3987 /* extpdp */, 2 /* 1 */, MCK_ACC64DSPAsmReg, AMFBS_HasDSP },
9772 { 3987 /* extpdp */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasDSP },
9775 { 3994 /* extpdpv */, 2 /* 1 */, MCK_ACC64DSPAsmReg, AMFBS_HasDSP },
9776 { 3994 /* extpdpv */, 5 /* 0, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSP },
9779 { 4002 /* extpv */, 2 /* 1 */, MCK_ACC64DSPAsmReg, AMFBS_HasDSP },
9780 { 4002 /* extpv */, 5 /* 0, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSP },
9783 { 4008 /* extr.w */, 2 /* 1 */, MCK_ACC64DSPAsmReg, AMFBS_HasDSP },
9784 { 4008 /* extr.w */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasDSP },
9787 { 4015 /* extr_r.w */, 2 /* 1 */, MCK_ACC64DSPAsmReg, AMFBS_HasDSP },
9788 { 4015 /* extr_r.w */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasDSP },
9791 { 4024 /* extr_rs.w */, 2 /* 1 */, MCK_ACC64DSPAsmReg, AMFBS_HasDSP },
9792 { 4024 /* extr_rs.w */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasDSP },
9795 { 4034 /* extr_s.h */, 2 /* 1 */, MCK_ACC64DSPAsmReg, AMFBS_HasDSP },
9796 { 4034 /* extr_s.h */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasDSP },
9799 { 4043 /* extrv.w */, 2 /* 1 */, MCK_ACC64DSPAsmReg, AMFBS_HasDSP },
9800 { 4043 /* extrv.w */, 5 /* 0, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSP },
9803 { 4051 /* extrv_r.w */, 2 /* 1 */, MCK_ACC64DSPAsmReg, AMFBS_HasDSP },
9804 { 4051 /* extrv_r.w */, 5 /* 0, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSP },
9807 { 4061 /* extrv_rs.w */, 2 /* 1 */, MCK_ACC64DSPAsmReg, AMFBS_HasDSP },
9808 { 4061 /* extrv_rs.w */, 5 /* 0, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSP },
9811 { 4072 /* extrv_s.h */, 2 /* 1 */, MCK_ACC64DSPAsmReg, AMFBS_HasDSP },
9812 { 4072 /* extrv_s.h */, 5 /* 0, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSP },
9991 { 5261 /* insv */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasDSP },
10083 { 5449 /* lbux */, 11 /* 0, 1, 3 */, MCK_GPR32AsmReg, AMFBS_HasDSP },
10145 { 5557 /* lhx */, 11 /* 0, 1, 3 */, MCK_GPR32AsmReg, AMFBS_HasDSP },
10252 { 5684 /* lwx */, 11 /* 0, 1, 3 */, MCK_GPR32AsmReg, AMFBS_HasDSP },
10262 { 5699 /* madd */, 1 /* 0 */, MCK_ACC64DSPAsmReg, AMFBS_HasDSP },
10263 { 5699 /* madd */, 6 /* 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSP },
10281 { 5772 /* maddu */, 1 /* 0 */, MCK_ACC64DSPAsmReg, AMFBS_HasDSP },
10282 { 5772 /* maddu */, 6 /* 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSP },
10289 { 5810 /* maq_s.w.phl */, 1 /* 0 */, MCK_ACC64DSPAsmReg, AMFBS_HasDSP },
10290 { 5810 /* maq_s.w.phl */, 6 /* 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSP },
10293 { 5822 /* maq_s.w.phr */, 1 /* 0 */, MCK_ACC64DSPAsmReg, AMFBS_HasDSP },
10294 { 5822 /* maq_s.w.phr */, 6 /* 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSP },
10297 { 5834 /* maq_sa.w.phl */, 1 /* 0 */, MCK_ACC64DSPAsmReg, AMFBS_HasDSP },
10298 { 5834 /* maq_sa.w.phl */, 6 /* 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSP },
10301 { 5847 /* maq_sa.w.phr */, 1 /* 0 */, MCK_ACC64DSPAsmReg, AMFBS_HasDSP },
10302 { 5847 /* maq_sa.w.phr */, 6 /* 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSP },
10387 { 6100 /* mfhi */, 2 /* 1 */, MCK_ACC64DSPAsmReg, AMFBS_HasDSP },
10388 { 6100 /* mfhi */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasDSP },
10394 { 6112 /* mflo */, 2 /* 1 */, MCK_ACC64DSPAsmReg, AMFBS_HasDSP },
10395 { 6112 /* mflo */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasDSP },
10456 { 6443 /* modsub */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSP },
10536 { 6568 /* msub */, 1 /* 0 */, MCK_ACC64DSPAsmReg, AMFBS_HasDSP },
10537 { 6568 /* msub */, 6 /* 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSP },
10555 { 6641 /* msubu */, 1 /* 0 */, MCK_ACC64DSPAsmReg, AMFBS_HasDSP },
10556 { 6641 /* msubu */, 6 /* 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSP },
10619 { 6725 /* mthi */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasDSP },
10620 { 6725 /* mthi */, 2 /* 1 */, MCK_HI32DSPAsmReg, AMFBS_HasDSP },
10623 { 6730 /* mthlip */, 2 /* 1 */, MCK_ACC64DSPAsmReg, AMFBS_HasDSP },
10624 { 6730 /* mthlip */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasDSP },
10629 { 6737 /* mtlo */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasDSP },
10630 { 6737 /* mtlo */, 2 /* 1 */, MCK_LO32DSPAsmReg, AMFBS_HasDSP },
10685 { 6886 /* muleq_s.w.phl */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSP },
10687 { 6900 /* muleq_s.w.phr */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSP },
10689 { 6914 /* muleu_s.ph.qbl */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSP },
10691 { 6929 /* muleu_s.ph.qbr */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSP },
10697 { 6955 /* mulq_rs.ph */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSP },
10712 { 7024 /* mulsaq_s.w.ph */, 1 /* 0 */, MCK_ACC64DSPAsmReg, AMFBS_HasDSP },
10713 { 7024 /* mulsaq_s.w.ph */, 6 /* 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSP },
10718 { 7038 /* mult */, 1 /* 0 */, MCK_ACC64DSPAsmReg, AMFBS_HasDSP },
10719 { 7038 /* mult */, 6 /* 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSP },
10724 { 7043 /* multu */, 1 /* 0 */, MCK_ACC64DSPAsmReg, AMFBS_HasDSP },
10725 { 7043 /* multu */, 6 /* 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSP },
10812 { 7245 /* packrl.ph */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSP },
10826 { 7353 /* pick.ph */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSP },
10828 { 7361 /* pick.qb */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSP },
10834 { 7387 /* preceq.w.phl */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasDSP },
10836 { 7400 /* preceq.w.phr */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasDSP },
10838 { 7413 /* precequ.ph.qbl */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasDSP },
10840 { 7428 /* precequ.ph.qbla */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasDSP },
10842 { 7444 /* precequ.ph.qbr */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasDSP },
10844 { 7459 /* precequ.ph.qbra */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasDSP },
10846 { 7475 /* preceu.ph.qbl */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasDSP },
10848 { 7489 /* preceu.ph.qbla */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasDSP },
10850 { 7504 /* preceu.ph.qbr */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasDSP },
10852 { 7518 /* preceu.ph.qbra */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasDSP },
10860 { 7577 /* precrq.ph.w */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSP },
10862 { 7589 /* precrq.qb.ph */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSP },
10864 { 7602 /* precrq_rs.ph.w */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSP },
10866 { 7617 /* precrqu_s.qb.ph */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSP },
10877 { 7658 /* raddu.w.qb */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasDSP },
10879 { 7669 /* rddsp */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasDSP },
10910 { 7713 /* repl.ph */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasDSP },
10912 { 7721 /* repl.qb */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasDSP },
10914 { 7729 /* replv.ph */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasDSP },
10916 { 7738 /* replv.qb */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasDSP },
11118 { 8104 /* shilo */, 1 /* 0 */, MCK_ACC64DSPAsmReg, AMFBS_HasDSP },
11121 { 8110 /* shilov */, 1 /* 0 */, MCK_ACC64DSPAsmReg, AMFBS_HasDSP },
11122 { 8110 /* shilov */, 2 /* 1 */, MCK_GPR32AsmReg, AMFBS_HasDSP },
11124 { 8117 /* shll.ph */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasDSP },
11126 { 8125 /* shll.qb */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasDSP },
11128 { 8133 /* shll_s.ph */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasDSP },
11130 { 8143 /* shll_s.w */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasDSP },
11132 { 8152 /* shllv.ph */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSP },
11134 { 8161 /* shllv.qb */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSP },
11136 { 8170 /* shllv_s.ph */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSP },
11138 { 8181 /* shllv_s.w */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSP },
11140 { 8191 /* shra.ph */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasDSP },
11144 { 8207 /* shra_r.ph */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasDSP },
11148 { 8227 /* shra_r.w */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasDSP },
11150 { 8236 /* shrav.ph */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSP },
11154 { 8254 /* shrav_r.ph */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSP },
11158 { 8276 /* shrav_r.w */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSP },
11162 { 8294 /* shrl.qb */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasDSP },
11166 { 8311 /* shrlv.qb */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSP },
11326 { 8847 /* subq.ph */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSP },
11328 { 8855 /* subq_s.ph */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSP },
11330 { 8865 /* subq_s.w */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSP },
11368 { 9085 /* subu.qb */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSP },
11374 { 9110 /* subu_s.qb */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSP },