|
|
reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
|
References
gen/lib/Target/Hexagon/HexagonGenRegisterInfo.inc 2372 { 1, 1, 0, VTLists+0 }, // UsrBits
2373 { 32, 32, 32, VTLists+8 }, // GuestRegs
2374 { 32, 32, 32, VTLists+22 }, // IntRegs
2375 { 32, 32, 32, VTLists+8 }, // CtrRegs
2376 { 32, 32, 32, VTLists+8 }, // GeneralSubRegs
2377 { 32, 32, 32, VTLists+8 }, // V62Regs
2378 { 32, 32, 32, VTLists+8 }, // IntRegsLow8
2379 { 32, 32, 32, VTLists+8 }, // CtrRegs_and_V62Regs
2380 { 32, 32, 32, VTLists+2 }, // PredRegs
2381 { 32, 32, 32, VTLists+8 }, // V62Regs_with_isub_hi
2382 { 32, 32, 32, VTLists+8 }, // ModRegs
2383 { 32, 32, 32, VTLists+8 }, // CtrRegs_with_subreg_overflow
2384 { 32, 32, 32, VTLists+8 }, // V65Regs
2385 { 64, 64, 64, VTLists+27 }, // DoubleRegs
2386 { 64, 64, 64, VTLists+10 }, // GuestRegs64
2387 { 64, 64, 64, VTLists+10 }, // CtrRegs64
2388 { 64, 64, 64, VTLists+10 }, // GeneralDoubleLow8Regs
2389 { 64, 64, 64, VTLists+10 }, // DoubleRegs_with_isub_hi_in_IntRegsLow8
2390 { 64, 64, 64, VTLists+10 }, // CtrRegs64_and_V62Regs
2391 { 64, 64, 64, VTLists+10 }, // CtrRegs64_with_isub_hi_in_ModRegs
2392 { 512, 512, 512, VTLists+33 }, // HvxVR
2393 { 512, 512, 512, VTLists+12 }, // HvxQR
2394 { 512, 512, 512, VTLists+33 }, // HvxVR_and_V65Regs
2395 { 1024, 1024, 1024, VTLists+37 }, // HvxWR
2396 { 2048, 2048, 2048, VTLists+45 }, // HvxVQR
2398 { 1, 1, 0, VTLists+0 }, // UsrBits
2399 { 32, 32, 32, VTLists+8 }, // GuestRegs
2400 { 32, 32, 32, VTLists+22 }, // IntRegs
2401 { 32, 32, 32, VTLists+8 }, // CtrRegs
2402 { 32, 32, 32, VTLists+8 }, // GeneralSubRegs
2403 { 32, 32, 32, VTLists+8 }, // V62Regs
2404 { 32, 32, 32, VTLists+8 }, // IntRegsLow8
2405 { 32, 32, 32, VTLists+8 }, // CtrRegs_and_V62Regs
2406 { 32, 32, 32, VTLists+2 }, // PredRegs
2407 { 32, 32, 32, VTLists+8 }, // V62Regs_with_isub_hi
2408 { 32, 32, 32, VTLists+8 }, // ModRegs
2409 { 32, 32, 32, VTLists+8 }, // CtrRegs_with_subreg_overflow
2410 { 32, 32, 32, VTLists+8 }, // V65Regs
2411 { 64, 64, 64, VTLists+27 }, // DoubleRegs
2412 { 64, 64, 64, VTLists+10 }, // GuestRegs64
2413 { 64, 64, 64, VTLists+10 }, // CtrRegs64
2414 { 64, 64, 64, VTLists+10 }, // GeneralDoubleLow8Regs
2415 { 64, 64, 64, VTLists+10 }, // DoubleRegs_with_isub_hi_in_IntRegsLow8
2416 { 64, 64, 64, VTLists+10 }, // CtrRegs64_and_V62Regs
2417 { 64, 64, 64, VTLists+10 }, // CtrRegs64_with_isub_hi_in_ModRegs
2418 { 1024, 1024, 1024, VTLists+37 }, // HvxVR
2419 { 1024, 1024, 1024, VTLists+17 }, // HvxQR
2420 { 1024, 1024, 1024, VTLists+37 }, // HvxVR_and_V65Regs
2421 { 2048, 2048, 2048, VTLists+41 }, // HvxWR
2422 { 4096, 4096, 4096, VTLists+45 }, // HvxVQR
2424 { 1, 1, 0, VTLists+0 }, // UsrBits
2425 { 32, 32, 32, VTLists+8 }, // GuestRegs
2426 { 32, 32, 32, VTLists+22 }, // IntRegs
2427 { 32, 32, 32, VTLists+8 }, // CtrRegs
2428 { 32, 32, 32, VTLists+8 }, // GeneralSubRegs
2429 { 32, 32, 32, VTLists+8 }, // V62Regs
2430 { 32, 32, 32, VTLists+8 }, // IntRegsLow8
2431 { 32, 32, 32, VTLists+8 }, // CtrRegs_and_V62Regs
2432 { 32, 32, 32, VTLists+2 }, // PredRegs
2433 { 32, 32, 32, VTLists+8 }, // V62Regs_with_isub_hi
2434 { 32, 32, 32, VTLists+8 }, // ModRegs
2435 { 32, 32, 32, VTLists+8 }, // CtrRegs_with_subreg_overflow
2436 { 32, 32, 32, VTLists+8 }, // V65Regs
2437 { 64, 64, 64, VTLists+27 }, // DoubleRegs
2438 { 64, 64, 64, VTLists+10 }, // GuestRegs64
2439 { 64, 64, 64, VTLists+10 }, // CtrRegs64
2440 { 64, 64, 64, VTLists+10 }, // GeneralDoubleLow8Regs
2441 { 64, 64, 64, VTLists+10 }, // DoubleRegs_with_isub_hi_in_IntRegsLow8
2442 { 64, 64, 64, VTLists+10 }, // CtrRegs64_and_V62Regs
2443 { 64, 64, 64, VTLists+10 }, // CtrRegs64_with_isub_hi_in_ModRegs
2444 { 512, 512, 512, VTLists+33 }, // HvxVR
2445 { 512, 512, 512, VTLists+12 }, // HvxQR
2446 { 512, 512, 512, VTLists+33 }, // HvxVR_and_V65Regs
2447 { 1024, 1024, 1024, VTLists+37 }, // HvxWR
2448 { 2048, 2048, 2048, VTLists+45 }, // HvxVQR