reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced

References

gen/lib/Target/Hexagon/HexagonGenInstrInfo.inc

 3401 static const MCOperandInfo OperandInfo61[] = { { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, ((1 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { Hexagon::ModRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
 3402 static const MCOperandInfo OperandInfo62[] = { { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, ((1 << 16) | (1 << MCOI::TIED_TO)) }, { Hexagon::ModRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
 3403 static const MCOperandInfo OperandInfo63[] = { { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, ((1 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { Hexagon::ModRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
 3404 static const MCOperandInfo OperandInfo64[] = { { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, ((1 << 16) | (1 << MCOI::TIED_TO)) }, { Hexagon::ModRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
 3407 static const MCOperandInfo OperandInfo67[] = { { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { Hexagon::ModRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
 3408 static const MCOperandInfo OperandInfo68[] = { { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { Hexagon::ModRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
 3409 static const MCOperandInfo OperandInfo69[] = { { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { Hexagon::ModRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
 3410 static const MCOperandInfo OperandInfo70[] = { { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { Hexagon::ModRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
 3455 static const MCOperandInfo OperandInfo115[] = { { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::ModRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::HvxVRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
 3456 static const MCOperandInfo OperandInfo116[] = { { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::HvxQRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::ModRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::HvxVRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
 3457 static const MCOperandInfo OperandInfo117[] = { { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::ModRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::HvxWRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
 3458 static const MCOperandInfo OperandInfo118[] = { { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::HvxQRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::ModRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::HvxWRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
 3466 static const MCOperandInfo OperandInfo126[] = { { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::ModRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::HvxVRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::HvxVRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
 3467 static const MCOperandInfo OperandInfo127[] = { { Hexagon::HvxQRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::ModRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::HvxVRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::HvxVRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
 3468 static const MCOperandInfo OperandInfo128[] = { { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::ModRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::HvxWRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::HvxVRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
 3469 static const MCOperandInfo OperandInfo129[] = { { Hexagon::HvxQRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::ModRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::HvxWRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::HvxVRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
 3513 static const MCOperandInfo OperandInfo173[] = { { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, ((1 << 16) | (1 << MCOI::TIED_TO)) }, { Hexagon::ModRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
 3514 static const MCOperandInfo OperandInfo174[] = { { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, ((1 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { Hexagon::ModRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
 3516 static const MCOperandInfo OperandInfo176[] = { { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, ((1 << 16) | (1 << MCOI::TIED_TO)) }, { Hexagon::ModRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
 3517 static const MCOperandInfo OperandInfo177[] = { { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, ((1 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { Hexagon::ModRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
 3519 static const MCOperandInfo OperandInfo179[] = { { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, ((1 << 16) | (1 << MCOI::TIED_TO)) }, { Hexagon::ModRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
 3520 static const MCOperandInfo OperandInfo180[] = { { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, ((1 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { Hexagon::ModRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
 3533 static const MCOperandInfo OperandInfo193[] = { { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::ModRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
 3550 static const MCOperandInfo OperandInfo210[] = { { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { Hexagon::ModRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
 3551 static const MCOperandInfo OperandInfo211[] = { { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { Hexagon::ModRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
 3554 static const MCOperandInfo OperandInfo214[] = { { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { Hexagon::ModRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
 3555 static const MCOperandInfo OperandInfo215[] = { { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { Hexagon::ModRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::DoubleRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
 3585 static const MCOperandInfo OperandInfo245[] = { { Hexagon::HvxVRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, ((1 << 16) | (1 << MCOI::TIED_TO)) }, { Hexagon::ModRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
 3588 static const MCOperandInfo OperandInfo248[] = { { Hexagon::HvxVRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::PredRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, ((1 << 16) | (1 << MCOI::TIED_TO)) }, { Hexagon::ModRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
 3592 static const MCOperandInfo OperandInfo252[] = { { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::PredRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { Hexagon::ModRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::HvxVRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
 3594 static const MCOperandInfo OperandInfo254[] = { { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { Hexagon::ModRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::HvxVRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
 3597 static const MCOperandInfo OperandInfo257[] = { { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::HvxQRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { Hexagon::ModRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::HvxVRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
 3598 static const MCOperandInfo OperandInfo258[] = { { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { Hexagon::ModRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
 3607 static const MCOperandInfo OperandInfo267[] = { { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::ModRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::HvxVRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
 3608 static const MCOperandInfo OperandInfo268[] = { { Hexagon::HvxQRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::ModRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::HvxVRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
 3609 static const MCOperandInfo OperandInfo269[] = { { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::ModRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::HvxWRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
 3610 static const MCOperandInfo OperandInfo270[] = { { Hexagon::HvxQRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::ModRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::HvxWRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
 3627 static const MCOperandInfo OperandInfo287[] = { { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::PredRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Hexagon::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { Hexagon::ModRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };

gen/lib/Target/Hexagon/HexagonGenRegisterInfo.inc

 1290   { ModRegs, ModRegsBits, 239, 2, sizeof(ModRegsBits), Hexagon::ModRegsRegClassID, 1, true },
 2767     &HexagonMCRegisterClasses[ModRegsRegClassID],