|
|
reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
|
References
gen/lib/Target/Hexagon/HexagonGenInstrInfo.inc 4078 { 448, 3, 1, 4, 2, 0|(1ULL<<MCID::Pseudo), 0x8027ULL, nullptr, nullptr, OperandInfo96, -1 ,nullptr }, // Inst #448 = V6_vabsdiffh_alt
4079 { 449, 3, 1, 4, 2, 0|(1ULL<<MCID::Pseudo), 0x8027ULL, nullptr, nullptr, OperandInfo96, -1 ,nullptr }, // Inst #449 = V6_vabsdiffub_alt
4080 { 450, 3, 1, 4, 2, 0|(1ULL<<MCID::Pseudo), 0x8027ULL, nullptr, nullptr, OperandInfo96, -1 ,nullptr }, // Inst #450 = V6_vabsdiffuh_alt
4081 { 451, 3, 1, 4, 2, 0|(1ULL<<MCID::Pseudo), 0x8027ULL, nullptr, nullptr, OperandInfo96, -1 ,nullptr }, // Inst #451 = V6_vabsdiffw_alt
4089 { 459, 3, 1, 4, 2, 0|(1ULL<<MCID::Pseudo), 0x8027ULL, nullptr, nullptr, OperandInfo96, -1 ,nullptr }, // Inst #459 = V6_vaddb_alt
4093 { 463, 3, 1, 4, 2, 0|(1ULL<<MCID::Pseudo), 0x8027ULL, nullptr, nullptr, OperandInfo96, -1 ,nullptr }, // Inst #463 = V6_vaddbsat_alt
4095 { 465, 3, 1, 4, 2, 0|(1ULL<<MCID::Pseudo), 0x8027ULL, nullptr, nullptr, OperandInfo96, -1 ,nullptr }, // Inst #465 = V6_vaddh_alt
4099 { 469, 3, 1, 4, 2, 0|(1ULL<<MCID::Pseudo), 0x8027ULL, nullptr, nullptr, OperandInfo96, -1 ,nullptr }, // Inst #469 = V6_vaddhsat_alt
4105 { 475, 3, 1, 4, 2, 0|(1ULL<<MCID::Pseudo), 0x8027ULL, nullptr, nullptr, OperandInfo96, -1 ,nullptr }, // Inst #475 = V6_vaddubsat_alt
4107 { 477, 3, 1, 4, 2, 0|(1ULL<<MCID::Pseudo), 0x8027ULL, nullptr, nullptr, OperandInfo96, -1 ,nullptr }, // Inst #477 = V6_vadduhsat_alt
4111 { 481, 3, 1, 4, 2, 0|(1ULL<<MCID::Pseudo), 0x8027ULL, nullptr, nullptr, OperandInfo96, -1 ,nullptr }, // Inst #481 = V6_vadduwsat_alt
4113 { 483, 3, 1, 4, 2, 0|(1ULL<<MCID::Pseudo), 0x8027ULL, nullptr, nullptr, OperandInfo96, -1 ,nullptr }, // Inst #483 = V6_vaddw_alt
4117 { 487, 3, 1, 4, 2, 0|(1ULL<<MCID::Pseudo), 0x8027ULL, nullptr, nullptr, OperandInfo96, -1 ,nullptr }, // Inst #487 = V6_vaddwsat_alt
4127 { 497, 3, 1, 4, 2, 0|(1ULL<<MCID::Pseudo), 0x8027ULL, nullptr, nullptr, OperandInfo96, -1 ,nullptr }, // Inst #497 = V6_vaslhv_alt
4130 { 500, 3, 1, 4, 2, 0|(1ULL<<MCID::Pseudo), 0x8027ULL, nullptr, nullptr, OperandInfo96, -1 ,nullptr }, // Inst #500 = V6_vaslwv_alt
4137 { 507, 3, 1, 4, 2, 0|(1ULL<<MCID::Pseudo), 0x8027ULL, nullptr, nullptr, OperandInfo96, -1 ,nullptr }, // Inst #507 = V6_vasrhv_alt
4144 { 514, 3, 1, 4, 2, 0|(1ULL<<MCID::Pseudo), 0x8027ULL, nullptr, nullptr, OperandInfo96, -1 ,nullptr }, // Inst #514 = V6_vasrwv_alt
4146 { 516, 3, 1, 4, 2, 0|(1ULL<<MCID::Pseudo), 0x8027ULL, nullptr, nullptr, OperandInfo96, -1 ,nullptr }, // Inst #516 = V6_vavgb_alt
4147 { 517, 3, 1, 4, 2, 0|(1ULL<<MCID::Pseudo), 0x8027ULL, nullptr, nullptr, OperandInfo96, -1 ,nullptr }, // Inst #517 = V6_vavgbrnd_alt
4148 { 518, 3, 1, 4, 2, 0|(1ULL<<MCID::Pseudo), 0x8027ULL, nullptr, nullptr, OperandInfo96, -1 ,nullptr }, // Inst #518 = V6_vavgh_alt
4149 { 519, 3, 1, 4, 2, 0|(1ULL<<MCID::Pseudo), 0x8027ULL, nullptr, nullptr, OperandInfo96, -1 ,nullptr }, // Inst #519 = V6_vavghrnd_alt
4150 { 520, 3, 1, 4, 2, 0|(1ULL<<MCID::Pseudo), 0x8027ULL, nullptr, nullptr, OperandInfo96, -1 ,nullptr }, // Inst #520 = V6_vavgub_alt
4151 { 521, 3, 1, 4, 2, 0|(1ULL<<MCID::Pseudo), 0x8027ULL, nullptr, nullptr, OperandInfo96, -1 ,nullptr }, // Inst #521 = V6_vavgubrnd_alt
4152 { 522, 3, 1, 4, 2, 0|(1ULL<<MCID::Pseudo), 0x8027ULL, nullptr, nullptr, OperandInfo96, -1 ,nullptr }, // Inst #522 = V6_vavguh_alt
4153 { 523, 3, 1, 4, 2, 0|(1ULL<<MCID::Pseudo), 0x8027ULL, nullptr, nullptr, OperandInfo96, -1 ,nullptr }, // Inst #523 = V6_vavguhrnd_alt
4154 { 524, 3, 1, 4, 2, 0|(1ULL<<MCID::Pseudo), 0x8027ULL, nullptr, nullptr, OperandInfo96, -1 ,nullptr }, // Inst #524 = V6_vavguw_alt
4155 { 525, 3, 1, 4, 2, 0|(1ULL<<MCID::Pseudo), 0x8027ULL, nullptr, nullptr, OperandInfo96, -1 ,nullptr }, // Inst #525 = V6_vavguwrnd_alt
4156 { 526, 3, 1, 4, 2, 0|(1ULL<<MCID::Pseudo), 0x8027ULL, nullptr, nullptr, OperandInfo96, -1 ,nullptr }, // Inst #526 = V6_vavgw_alt
4157 { 527, 3, 1, 4, 2, 0|(1ULL<<MCID::Pseudo), 0x8027ULL, nullptr, nullptr, OperandInfo96, -1 ,nullptr }, // Inst #527 = V6_vavgwrnd_alt
4162 { 532, 3, 1, 4, 2, 0|(1ULL<<MCID::Pseudo), 0x8027ULL, nullptr, nullptr, OperandInfo96, -1 ,nullptr }, // Inst #532 = V6_vdealb4w_alt
4182 { 552, 3, 1, 4, 2, 0|(1ULL<<MCID::Pseudo), 0x8027ULL, nullptr, nullptr, OperandInfo96, -1 ,nullptr }, // Inst #552 = V6_vdmpyhvsat_alt
4192 { 562, 3, 1, 4, 2, 0|(1ULL<<MCID::Pseudo), 0x8027ULL, nullptr, nullptr, OperandInfo96, -1 ,nullptr }, // Inst #562 = V6_vlsrhv_alt
4194 { 564, 3, 1, 4, 2, 0|(1ULL<<MCID::Pseudo), 0x8027ULL, nullptr, nullptr, OperandInfo96, -1 ,nullptr }, // Inst #564 = V6_vlsrwv_alt
4195 { 565, 3, 1, 4, 2, 0|(1ULL<<MCID::Pseudo), 0x8027ULL, nullptr, nullptr, OperandInfo96, -1 ,nullptr }, // Inst #565 = V6_vmaxb_alt
4196 { 566, 3, 1, 4, 2, 0|(1ULL<<MCID::Pseudo), 0x8027ULL, nullptr, nullptr, OperandInfo96, -1 ,nullptr }, // Inst #566 = V6_vmaxh_alt
4197 { 567, 3, 1, 4, 2, 0|(1ULL<<MCID::Pseudo), 0x8027ULL, nullptr, nullptr, OperandInfo96, -1 ,nullptr }, // Inst #567 = V6_vmaxub_alt
4198 { 568, 3, 1, 4, 2, 0|(1ULL<<MCID::Pseudo), 0x8027ULL, nullptr, nullptr, OperandInfo96, -1 ,nullptr }, // Inst #568 = V6_vmaxuh_alt
4199 { 569, 3, 1, 4, 2, 0|(1ULL<<MCID::Pseudo), 0x8027ULL, nullptr, nullptr, OperandInfo96, -1 ,nullptr }, // Inst #569 = V6_vmaxw_alt
4200 { 570, 3, 1, 4, 2, 0|(1ULL<<MCID::Pseudo), 0x8027ULL, nullptr, nullptr, OperandInfo96, -1 ,nullptr }, // Inst #570 = V6_vminb_alt
4201 { 571, 3, 1, 4, 2, 0|(1ULL<<MCID::Pseudo), 0x8027ULL, nullptr, nullptr, OperandInfo96, -1 ,nullptr }, // Inst #571 = V6_vminh_alt
4202 { 572, 3, 1, 4, 2, 0|(1ULL<<MCID::Pseudo), 0x8027ULL, nullptr, nullptr, OperandInfo96, -1 ,nullptr }, // Inst #572 = V6_vminub_alt
4203 { 573, 3, 1, 4, 2, 0|(1ULL<<MCID::Pseudo), 0x8027ULL, nullptr, nullptr, OperandInfo96, -1 ,nullptr }, // Inst #573 = V6_vminuh_alt
4204 { 574, 3, 1, 4, 2, 0|(1ULL<<MCID::Pseudo), 0x8027ULL, nullptr, nullptr, OperandInfo96, -1 ,nullptr }, // Inst #574 = V6_vminw_alt
4221 { 591, 3, 1, 4, 2, 0|(1ULL<<MCID::Pseudo), 0x8027ULL, nullptr, nullptr, OperandInfo96, -1 ,nullptr }, // Inst #591 = V6_vmpyewuh_alt
4231 { 601, 3, 1, 4, 2, 0|(1ULL<<MCID::Pseudo), 0x8027ULL, nullptr, nullptr, OperandInfo96, -1 ,nullptr }, // Inst #601 = V6_vmpyhvsrs_alt
4234 { 604, 3, 1, 4, 2, 0|(1ULL<<MCID::Pseudo), 0x8027ULL, nullptr, nullptr, OperandInfo96, -1 ,nullptr }, // Inst #604 = V6_vmpyiewuh_alt
4236 { 606, 3, 1, 4, 2, 0|(1ULL<<MCID::Pseudo), 0x8027ULL, nullptr, nullptr, OperandInfo96, -1 ,nullptr }, // Inst #606 = V6_vmpyih_alt
4239 { 609, 3, 1, 4, 2, 0|(1ULL<<MCID::Pseudo), 0x8027ULL, nullptr, nullptr, OperandInfo96, -1 ,nullptr }, // Inst #609 = V6_vmpyiowh_alt
4246 { 616, 3, 1, 4, 2, 0|(1ULL<<MCID::Pseudo), 0x8027ULL, nullptr, nullptr, OperandInfo96, -1 ,nullptr }, // Inst #616 = V6_vmpyowh_alt
4247 { 617, 3, 1, 4, 2, 0|(1ULL<<MCID::Pseudo), 0x8027ULL, nullptr, nullptr, OperandInfo96, -1 ,nullptr }, // Inst #617 = V6_vmpyowh_rnd_alt
4258 { 628, 3, 1, 4, 2, 0|(1ULL<<MCID::Pseudo), 0x8027ULL, nullptr, nullptr, OperandInfo96, -1 ,nullptr }, // Inst #628 = V6_vnavgb_alt
4259 { 629, 3, 1, 4, 2, 0|(1ULL<<MCID::Pseudo), 0x8027ULL, nullptr, nullptr, OperandInfo96, -1 ,nullptr }, // Inst #629 = V6_vnavgh_alt
4260 { 630, 3, 1, 4, 2, 0|(1ULL<<MCID::Pseudo), 0x8027ULL, nullptr, nullptr, OperandInfo96, -1 ,nullptr }, // Inst #630 = V6_vnavgub_alt
4261 { 631, 3, 1, 4, 2, 0|(1ULL<<MCID::Pseudo), 0x8027ULL, nullptr, nullptr, OperandInfo96, -1 ,nullptr }, // Inst #631 = V6_vnavgw_alt
4264 { 634, 3, 1, 4, 2, 0|(1ULL<<MCID::Pseudo), 0x8027ULL, nullptr, nullptr, OperandInfo96, -1 ,nullptr }, // Inst #634 = V6_vpackeb_alt
4265 { 635, 3, 1, 4, 2, 0|(1ULL<<MCID::Pseudo), 0x8027ULL, nullptr, nullptr, OperandInfo96, -1 ,nullptr }, // Inst #635 = V6_vpackeh_alt
4266 { 636, 3, 1, 4, 2, 0|(1ULL<<MCID::Pseudo), 0x8027ULL, nullptr, nullptr, OperandInfo96, -1 ,nullptr }, // Inst #636 = V6_vpackhb_sat_alt
4267 { 637, 3, 1, 4, 2, 0|(1ULL<<MCID::Pseudo), 0x8027ULL, nullptr, nullptr, OperandInfo96, -1 ,nullptr }, // Inst #637 = V6_vpackhub_sat_alt
4268 { 638, 3, 1, 4, 2, 0|(1ULL<<MCID::Pseudo), 0x8027ULL, nullptr, nullptr, OperandInfo96, -1 ,nullptr }, // Inst #638 = V6_vpackob_alt
4269 { 639, 3, 1, 4, 2, 0|(1ULL<<MCID::Pseudo), 0x8027ULL, nullptr, nullptr, OperandInfo96, -1 ,nullptr }, // Inst #639 = V6_vpackoh_alt
4270 { 640, 3, 1, 4, 2, 0|(1ULL<<MCID::Pseudo), 0x8027ULL, nullptr, nullptr, OperandInfo96, -1 ,nullptr }, // Inst #640 = V6_vpackwh_sat_alt
4271 { 641, 3, 1, 4, 2, 0|(1ULL<<MCID::Pseudo), 0x8027ULL, nullptr, nullptr, OperandInfo96, -1 ,nullptr }, // Inst #641 = V6_vpackwuh_sat_alt
4280 { 650, 3, 1, 4, 2, 0|(1ULL<<MCID::Pseudo), 0x8027ULL, nullptr, nullptr, OperandInfo96, -1 ,nullptr }, // Inst #650 = V6_vrmpybusv_alt
4282 { 652, 3, 1, 4, 2, 0|(1ULL<<MCID::Pseudo), 0x8027ULL, nullptr, nullptr, OperandInfo96, -1 ,nullptr }, // Inst #652 = V6_vrmpybv_alt
4290 { 660, 3, 1, 4, 2, 0|(1ULL<<MCID::Pseudo), 0x8027ULL, nullptr, nullptr, OperandInfo96, -1 ,nullptr }, // Inst #660 = V6_vrmpyubv_alt
4291 { 661, 3, 1, 4, 2, 0|(1ULL<<MCID::Pseudo), 0x8027ULL, nullptr, nullptr, OperandInfo96, -1 ,nullptr }, // Inst #661 = V6_vrotr_alt
4292 { 662, 3, 1, 4, 2, 0|(1ULL<<MCID::Pseudo), 0x8027ULL, nullptr, nullptr, OperandInfo96, -1 ,nullptr }, // Inst #662 = V6_vroundhb_alt
4293 { 663, 3, 1, 4, 2, 0|(1ULL<<MCID::Pseudo), 0x8027ULL, nullptr, nullptr, OperandInfo96, -1 ,nullptr }, // Inst #663 = V6_vroundhub_alt
4294 { 664, 3, 1, 4, 2, 0|(1ULL<<MCID::Pseudo), 0x8027ULL, nullptr, nullptr, OperandInfo96, -1 ,nullptr }, // Inst #664 = V6_vrounduhub_alt
4295 { 665, 3, 1, 4, 2, 0|(1ULL<<MCID::Pseudo), 0x8027ULL, nullptr, nullptr, OperandInfo96, -1 ,nullptr }, // Inst #665 = V6_vrounduwuh_alt
4296 { 666, 3, 1, 4, 2, 0|(1ULL<<MCID::Pseudo), 0x8027ULL, nullptr, nullptr, OperandInfo96, -1 ,nullptr }, // Inst #666 = V6_vroundwh_alt
4297 { 667, 3, 1, 4, 2, 0|(1ULL<<MCID::Pseudo), 0x8027ULL, nullptr, nullptr, OperandInfo96, -1 ,nullptr }, // Inst #667 = V6_vroundwuh_alt
4300 { 670, 3, 1, 4, 2, 0|(1ULL<<MCID::Pseudo), 0x8027ULL, nullptr, nullptr, OperandInfo96, -1 ,nullptr }, // Inst #670 = V6_vsathub_alt
4301 { 671, 3, 1, 4, 2, 0|(1ULL<<MCID::Pseudo), 0x8027ULL, nullptr, nullptr, OperandInfo96, -1 ,nullptr }, // Inst #671 = V6_vsatuwuh_alt
4302 { 672, 3, 1, 4, 2, 0|(1ULL<<MCID::Pseudo), 0x8027ULL, nullptr, nullptr, OperandInfo96, -1 ,nullptr }, // Inst #672 = V6_vsatwh_alt
4314 { 684, 3, 1, 4, 2, 0|(1ULL<<MCID::Pseudo), 0x8027ULL, nullptr, nullptr, OperandInfo96, -1 ,nullptr }, // Inst #684 = V6_vshufeh_alt
4316 { 686, 3, 1, 4, 2, 0|(1ULL<<MCID::Pseudo), 0x8027ULL, nullptr, nullptr, OperandInfo96, -1 ,nullptr }, // Inst #686 = V6_vshuffeb_alt
4318 { 688, 3, 1, 4, 2, 0|(1ULL<<MCID::Pseudo), 0x8027ULL, nullptr, nullptr, OperandInfo96, -1 ,nullptr }, // Inst #688 = V6_vshuffob_alt
4321 { 691, 3, 1, 4, 2, 0|(1ULL<<MCID::Pseudo), 0x8027ULL, nullptr, nullptr, OperandInfo96, -1 ,nullptr }, // Inst #691 = V6_vshufoh_alt
4322 { 692, 3, 1, 4, 2, 0|(1ULL<<MCID::Pseudo), 0x8027ULL, nullptr, nullptr, OperandInfo96, -1 ,nullptr }, // Inst #692 = V6_vsubb_alt
4326 { 696, 3, 1, 4, 2, 0|(1ULL<<MCID::Pseudo), 0x8027ULL, nullptr, nullptr, OperandInfo96, -1 ,nullptr }, // Inst #696 = V6_vsubbsat_alt
4328 { 698, 3, 1, 4, 2, 0|(1ULL<<MCID::Pseudo), 0x8027ULL, nullptr, nullptr, OperandInfo96, -1 ,nullptr }, // Inst #698 = V6_vsubh_alt
4332 { 702, 3, 1, 4, 2, 0|(1ULL<<MCID::Pseudo), 0x8027ULL, nullptr, nullptr, OperandInfo96, -1 ,nullptr }, // Inst #702 = V6_vsubhsat_alt
4336 { 706, 3, 1, 4, 2, 0|(1ULL<<MCID::Pseudo), 0x8027ULL, nullptr, nullptr, OperandInfo96, -1 ,nullptr }, // Inst #706 = V6_vsububsat_alt
4338 { 708, 3, 1, 4, 2, 0|(1ULL<<MCID::Pseudo), 0x8027ULL, nullptr, nullptr, OperandInfo96, -1 ,nullptr }, // Inst #708 = V6_vsubuhsat_alt
4341 { 711, 3, 1, 4, 2, 0|(1ULL<<MCID::Pseudo), 0x8027ULL, nullptr, nullptr, OperandInfo96, -1 ,nullptr }, // Inst #711 = V6_vsubuwsat_alt
4343 { 713, 3, 1, 4, 2, 0|(1ULL<<MCID::Pseudo), 0x8027ULL, nullptr, nullptr, OperandInfo96, -1 ,nullptr }, // Inst #713 = V6_vsubw_alt
4347 { 717, 3, 1, 4, 2, 0|(1ULL<<MCID::Pseudo), 0x8027ULL, nullptr, nullptr, OperandInfo96, -1 ,nullptr }, // Inst #717 = V6_vsubwsat_alt
6174 { 2544, 3, 1, 4, 207, 0, 0x801dULL, nullptr, nullptr, OperandInfo96, -1 ,nullptr }, // Inst #2544 = V6_vabsdiffh
6175 { 2545, 3, 1, 4, 207, 0, 0x801dULL, nullptr, nullptr, OperandInfo96, -1 ,nullptr }, // Inst #2545 = V6_vabsdiffub
6176 { 2546, 3, 1, 4, 207, 0, 0x801dULL, nullptr, nullptr, OperandInfo96, -1 ,nullptr }, // Inst #2546 = V6_vabsdiffuh
6177 { 2547, 3, 1, 4, 207, 0, 0x801dULL, nullptr, nullptr, OperandInfo96, -1 ,nullptr }, // Inst #2547 = V6_vabsdiffw
6182 { 2552, 3, 1, 4, 35, 0, 0x8010ULL, nullptr, nullptr, OperandInfo96, -1 ,nullptr }, // Inst #2552 = V6_vaddb
6186 { 2556, 3, 1, 4, 35, 0, 0x8010ULL, nullptr, nullptr, OperandInfo96, -1 ,nullptr }, // Inst #2556 = V6_vaddbsat
6191 { 2561, 3, 1, 4, 211, 0, 0x801bULL, nullptr, nullptr, OperandInfo96, -1 ,nullptr }, // Inst #2561 = V6_vaddclbh
6192 { 2562, 3, 1, 4, 211, 0, 0x801bULL, nullptr, nullptr, OperandInfo96, -1 ,nullptr }, // Inst #2562 = V6_vaddclbw
6193 { 2563, 3, 1, 4, 35, 0, 0x8010ULL, nullptr, nullptr, OperandInfo96, -1 ,nullptr }, // Inst #2563 = V6_vaddh
6197 { 2567, 3, 1, 4, 35, 0, 0x8010ULL, nullptr, nullptr, OperandInfo96, -1 ,nullptr }, // Inst #2567 = V6_vaddhsat
6203 { 2573, 3, 1, 4, 35, 0, 0x8010ULL, nullptr, nullptr, OperandInfo96, -1 ,nullptr }, // Inst #2573 = V6_vaddubsat
6205 { 2575, 3, 1, 4, 35, 0, 0x8010ULL, nullptr, nullptr, OperandInfo96, -1 ,nullptr }, // Inst #2575 = V6_vaddububb_sat
6206 { 2576, 3, 1, 4, 35, 0, 0x8010ULL, nullptr, nullptr, OperandInfo96, -1 ,nullptr }, // Inst #2576 = V6_vadduhsat
6210 { 2580, 3, 1, 4, 35, 0, 0x8010ULL, nullptr, nullptr, OperandInfo96, -1 ,nullptr }, // Inst #2580 = V6_vadduwsat
6212 { 2582, 3, 1, 4, 35, 0, 0x8010ULL, nullptr, nullptr, OperandInfo96, -1 ,nullptr }, // Inst #2582 = V6_vaddw
6216 { 2586, 3, 1, 4, 35, 0, 0x8010ULL, nullptr, nullptr, OperandInfo96, -1 ,nullptr }, // Inst #2586 = V6_vaddwsat
6220 { 2590, 3, 1, 4, 35, 0, 0x8010ULL, nullptr, nullptr, OperandInfo96, -1 ,nullptr }, // Inst #2590 = V6_vand
6231 { 2601, 3, 1, 4, 211, 0, 0x801bULL, nullptr, nullptr, OperandInfo96, -1 ,nullptr }, // Inst #2601 = V6_vaslhv
6234 { 2604, 3, 1, 4, 211, 0, 0x801bULL, nullptr, nullptr, OperandInfo96, -1 ,nullptr }, // Inst #2604 = V6_vaslwv
6242 { 2612, 3, 1, 4, 211, 0, 0x801bULL, nullptr, nullptr, OperandInfo96, -1 ,nullptr }, // Inst #2612 = V6_vasrhv
6254 { 2624, 3, 1, 4, 211, 0, 0x801bULL, nullptr, nullptr, OperandInfo96, -1 ,nullptr }, // Inst #2624 = V6_vasrwv
6256 { 2626, 3, 1, 4, 35, 0, 0x8010ULL, nullptr, nullptr, OperandInfo96, -1 ,nullptr }, // Inst #2626 = V6_vavgb
6257 { 2627, 3, 1, 4, 35, 0, 0x8010ULL, nullptr, nullptr, OperandInfo96, -1 ,nullptr }, // Inst #2627 = V6_vavgbrnd
6258 { 2628, 3, 1, 4, 35, 0, 0x8010ULL, nullptr, nullptr, OperandInfo96, -1 ,nullptr }, // Inst #2628 = V6_vavgh
6259 { 2629, 3, 1, 4, 35, 0, 0x8010ULL, nullptr, nullptr, OperandInfo96, -1 ,nullptr }, // Inst #2629 = V6_vavghrnd
6260 { 2630, 3, 1, 4, 35, 0, 0x8010ULL, nullptr, nullptr, OperandInfo96, -1 ,nullptr }, // Inst #2630 = V6_vavgub
6261 { 2631, 3, 1, 4, 35, 0, 0x8010ULL, nullptr, nullptr, OperandInfo96, -1 ,nullptr }, // Inst #2631 = V6_vavgubrnd
6262 { 2632, 3, 1, 4, 35, 0, 0x8010ULL, nullptr, nullptr, OperandInfo96, -1 ,nullptr }, // Inst #2632 = V6_vavguh
6263 { 2633, 3, 1, 4, 35, 0, 0x8010ULL, nullptr, nullptr, OperandInfo96, -1 ,nullptr }, // Inst #2633 = V6_vavguhrnd
6264 { 2634, 3, 1, 4, 35, 0, 0x8010ULL, nullptr, nullptr, OperandInfo96, -1 ,nullptr }, // Inst #2634 = V6_vavguw
6265 { 2635, 3, 1, 4, 35, 0, 0x8010ULL, nullptr, nullptr, OperandInfo96, -1 ,nullptr }, // Inst #2635 = V6_vavguwrnd
6266 { 2636, 3, 1, 4, 35, 0, 0x8010ULL, nullptr, nullptr, OperandInfo96, -1 ,nullptr }, // Inst #2636 = V6_vavgw
6267 { 2637, 3, 1, 4, 35, 0, 0x8010ULL, nullptr, nullptr, OperandInfo96, -1 ,nullptr }, // Inst #2637 = V6_vavgwrnd
6275 { 2645, 3, 1, 4, 223, 0, 0x8019ULL, nullptr, nullptr, OperandInfo96, -1 ,nullptr }, // Inst #2645 = V6_vdealb4w
6278 { 2648, 3, 1, 4, 223, 0, 0x8019ULL, nullptr, nullptr, OperandInfo96, -1 ,nullptr }, // Inst #2648 = V6_vdelta
6295 { 2665, 3, 1, 4, 212, 0, 0x801eULL, nullptr, nullptr, OperandInfo96, -1 ,nullptr }, // Inst #2665 = V6_vdmpyhvsat
6348 { 2718, 3, 1, 4, 211, 0, 0x801bULL, nullptr, nullptr, OperandInfo96, -1 ,nullptr }, // Inst #2718 = V6_vlsrhv
6350 { 2720, 3, 1, 4, 211, 0, 0x801bULL, nullptr, nullptr, OperandInfo96, -1 ,nullptr }, // Inst #2720 = V6_vlsrwv
6362 { 2732, 3, 1, 4, 35, 0, 0x8010ULL, nullptr, nullptr, OperandInfo96, -1 ,nullptr }, // Inst #2732 = V6_vmaxb
6363 { 2733, 3, 1, 4, 35, 0, 0x8010ULL, nullptr, nullptr, OperandInfo96, -1 ,nullptr }, // Inst #2733 = V6_vmaxh
6364 { 2734, 3, 1, 4, 35, 0, 0x8010ULL, nullptr, nullptr, OperandInfo96, -1 ,nullptr }, // Inst #2734 = V6_vmaxub
6365 { 2735, 3, 1, 4, 35, 0, 0x8010ULL, nullptr, nullptr, OperandInfo96, -1 ,nullptr }, // Inst #2735 = V6_vmaxuh
6366 { 2736, 3, 1, 4, 35, 0, 0x8010ULL, nullptr, nullptr, OperandInfo96, -1 ,nullptr }, // Inst #2736 = V6_vmaxw
6367 { 2737, 3, 1, 4, 35, 0, 0x8010ULL, nullptr, nullptr, OperandInfo96, -1 ,nullptr }, // Inst #2737 = V6_vminb
6368 { 2738, 3, 1, 4, 35, 0, 0x8010ULL, nullptr, nullptr, OperandInfo96, -1 ,nullptr }, // Inst #2738 = V6_vminh
6369 { 2739, 3, 1, 4, 35, 0, 0x8010ULL, nullptr, nullptr, OperandInfo96, -1 ,nullptr }, // Inst #2739 = V6_vminub
6370 { 2740, 3, 1, 4, 35, 0, 0x8010ULL, nullptr, nullptr, OperandInfo96, -1 ,nullptr }, // Inst #2740 = V6_vminuh
6371 { 2741, 3, 1, 4, 35, 0, 0x8010ULL, nullptr, nullptr, OperandInfo96, -1 ,nullptr }, // Inst #2741 = V6_vminw
6391 { 2761, 3, 1, 4, 212, 0, 0x801eULL, nullptr, nullptr, OperandInfo96, -1 ,nullptr }, // Inst #2761 = V6_vmpyewuh
6402 { 2772, 3, 1, 4, 212, 0, 0x801eULL, nullptr, nullptr, OperandInfo96, -1 ,nullptr }, // Inst #2772 = V6_vmpyhvsrs
6403 { 2773, 3, 1, 4, 207, 0, 0x801dULL, nullptr, nullptr, OperandInfo96, -1 ,nullptr }, // Inst #2773 = V6_vmpyieoh
6405 { 2775, 3, 1, 4, 212, 0, 0x801eULL, nullptr, nullptr, OperandInfo96, -1 ,nullptr }, // Inst #2775 = V6_vmpyiewuh
6407 { 2777, 3, 1, 4, 212, 0, 0x801eULL, nullptr, nullptr, OperandInfo96, -1 ,nullptr }, // Inst #2777 = V6_vmpyih
6411 { 2781, 3, 1, 4, 212, 0, 0x801eULL, nullptr, nullptr, OperandInfo96, -1 ,nullptr }, // Inst #2781 = V6_vmpyiowh
6418 { 2788, 3, 1, 4, 212, 0, 0x801eULL, nullptr, nullptr, OperandInfo96, -1 ,nullptr }, // Inst #2788 = V6_vmpyowh
6420 { 2790, 3, 1, 4, 212, 0, 0x801eULL, nullptr, nullptr, OperandInfo96, -1 ,nullptr }, // Inst #2790 = V6_vmpyowh_rnd
6434 { 2804, 3, 1, 4, 35, 0, 0x8010ULL, nullptr, nullptr, OperandInfo96, -1 ,nullptr }, // Inst #2804 = V6_vnavgb
6435 { 2805, 3, 1, 4, 35, 0, 0x8010ULL, nullptr, nullptr, OperandInfo96, -1 ,nullptr }, // Inst #2805 = V6_vnavgh
6436 { 2806, 3, 1, 4, 35, 0, 0x8010ULL, nullptr, nullptr, OperandInfo96, -1 ,nullptr }, // Inst #2806 = V6_vnavgub
6437 { 2807, 3, 1, 4, 35, 0, 0x8010ULL, nullptr, nullptr, OperandInfo96, -1 ,nullptr }, // Inst #2807 = V6_vnavgw
6443 { 2813, 3, 1, 4, 35, 0, 0x8010ULL, nullptr, nullptr, OperandInfo96, -1 ,nullptr }, // Inst #2813 = V6_vor
6444 { 2814, 3, 1, 4, 223, 0, 0x8019ULL, nullptr, nullptr, OperandInfo96, -1 ,nullptr }, // Inst #2814 = V6_vpackeb
6445 { 2815, 3, 1, 4, 223, 0, 0x8019ULL, nullptr, nullptr, OperandInfo96, -1 ,nullptr }, // Inst #2815 = V6_vpackeh
6446 { 2816, 3, 1, 4, 223, 0, 0x8019ULL, nullptr, nullptr, OperandInfo96, -1 ,nullptr }, // Inst #2816 = V6_vpackhb_sat
6447 { 2817, 3, 1, 4, 223, 0, 0x8019ULL, nullptr, nullptr, OperandInfo96, -1 ,nullptr }, // Inst #2817 = V6_vpackhub_sat
6448 { 2818, 3, 1, 4, 223, 0, 0x8019ULL, nullptr, nullptr, OperandInfo96, -1 ,nullptr }, // Inst #2818 = V6_vpackob
6449 { 2819, 3, 1, 4, 223, 0, 0x8019ULL, nullptr, nullptr, OperandInfo96, -1 ,nullptr }, // Inst #2819 = V6_vpackoh
6450 { 2820, 3, 1, 4, 223, 0, 0x8019ULL, nullptr, nullptr, OperandInfo96, -1 ,nullptr }, // Inst #2820 = V6_vpackwh_sat
6451 { 2821, 3, 1, 4, 223, 0, 0x8019ULL, nullptr, nullptr, OperandInfo96, -1 ,nullptr }, // Inst #2821 = V6_vpackwuh_sat
6456 { 2826, 3, 1, 4, 223, 0, 0x8019ULL, nullptr, nullptr, OperandInfo96, -1 ,nullptr }, // Inst #2826 = V6_vrdelta
6463 { 2833, 3, 1, 4, 207, 0, 0x801dULL, nullptr, nullptr, OperandInfo96, -1 ,nullptr }, // Inst #2833 = V6_vrmpybusv
6465 { 2835, 3, 1, 4, 207, 0, 0x801dULL, nullptr, nullptr, OperandInfo96, -1 ,nullptr }, // Inst #2835 = V6_vrmpybv
6473 { 2843, 3, 1, 4, 207, 0, 0x801dULL, nullptr, nullptr, OperandInfo96, -1 ,nullptr }, // Inst #2843 = V6_vrmpyubv
6496 { 2866, 3, 1, 4, 211, 0, 0x801bULL, nullptr, nullptr, OperandInfo96, -1 ,nullptr }, // Inst #2866 = V6_vrotr
6497 { 2867, 3, 1, 4, 211, 0, 0x801bULL, nullptr, nullptr, OperandInfo96, -1 ,nullptr }, // Inst #2867 = V6_vroundhb
6498 { 2868, 3, 1, 4, 211, 0, 0x801bULL, nullptr, nullptr, OperandInfo96, -1 ,nullptr }, // Inst #2868 = V6_vroundhub
6499 { 2869, 3, 1, 4, 211, 0, 0x801bULL, nullptr, nullptr, OperandInfo96, -1 ,nullptr }, // Inst #2869 = V6_vrounduhub
6500 { 2870, 3, 1, 4, 211, 0, 0x801bULL, nullptr, nullptr, OperandInfo96, -1 ,nullptr }, // Inst #2870 = V6_vrounduwuh
6501 { 2871, 3, 1, 4, 211, 0, 0x801bULL, nullptr, nullptr, OperandInfo96, -1 ,nullptr }, // Inst #2871 = V6_vroundwh
6502 { 2872, 3, 1, 4, 211, 0, 0x801bULL, nullptr, nullptr, OperandInfo96, -1 ,nullptr }, // Inst #2872 = V6_vroundwuh
6505 { 2875, 3, 1, 4, 35, 0, 0x8010ULL, nullptr, nullptr, OperandInfo96, -1 ,nullptr }, // Inst #2875 = V6_vsatdw
6506 { 2876, 3, 1, 4, 247, 0, 0x8012ULL, nullptr, nullptr, OperandInfo96, -1 ,nullptr }, // Inst #2876 = V6_vsathub
6507 { 2877, 3, 1, 4, 35, 0, 0x8010ULL, nullptr, nullptr, OperandInfo96, -1 ,nullptr }, // Inst #2877 = V6_vsatuwuh
6508 { 2878, 3, 1, 4, 247, 0, 0x8012ULL, nullptr, nullptr, OperandInfo96, -1 ,nullptr }, // Inst #2878 = V6_vsatwh
6520 { 2890, 3, 1, 4, 35, 0, 0x8010ULL, nullptr, nullptr, OperandInfo96, -1 ,nullptr }, // Inst #2890 = V6_vshufeh
6523 { 2893, 3, 1, 4, 35, 0, 0x8010ULL, nullptr, nullptr, OperandInfo96, -1 ,nullptr }, // Inst #2893 = V6_vshuffeb
6525 { 2895, 3, 1, 4, 35, 0, 0x8010ULL, nullptr, nullptr, OperandInfo96, -1 ,nullptr }, // Inst #2895 = V6_vshuffob
6529 { 2899, 3, 1, 4, 35, 0, 0x8010ULL, nullptr, nullptr, OperandInfo96, -1 ,nullptr }, // Inst #2899 = V6_vshufoh
6530 { 2900, 3, 1, 4, 35, 0, 0x8010ULL, nullptr, nullptr, OperandInfo96, -1 ,nullptr }, // Inst #2900 = V6_vsubb
6534 { 2904, 3, 1, 4, 35, 0, 0x8010ULL, nullptr, nullptr, OperandInfo96, -1 ,nullptr }, // Inst #2904 = V6_vsubbsat
6538 { 2908, 3, 1, 4, 35, 0, 0x8010ULL, nullptr, nullptr, OperandInfo96, -1 ,nullptr }, // Inst #2908 = V6_vsubh
6542 { 2912, 3, 1, 4, 35, 0, 0x8010ULL, nullptr, nullptr, OperandInfo96, -1 ,nullptr }, // Inst #2912 = V6_vsubhsat
6546 { 2916, 3, 1, 4, 35, 0, 0x8010ULL, nullptr, nullptr, OperandInfo96, -1 ,nullptr }, // Inst #2916 = V6_vsububsat
6548 { 2918, 3, 1, 4, 35, 0, 0x8010ULL, nullptr, nullptr, OperandInfo96, -1 ,nullptr }, // Inst #2918 = V6_vsubububb_sat
6549 { 2919, 3, 1, 4, 35, 0, 0x8010ULL, nullptr, nullptr, OperandInfo96, -1 ,nullptr }, // Inst #2919 = V6_vsubuhsat
6552 { 2922, 3, 1, 4, 35, 0, 0x8010ULL, nullptr, nullptr, OperandInfo96, -1 ,nullptr }, // Inst #2922 = V6_vsubuwsat
6554 { 2924, 3, 1, 4, 35, 0, 0x8010ULL, nullptr, nullptr, OperandInfo96, -1 ,nullptr }, // Inst #2924 = V6_vsubw
6558 { 2928, 3, 1, 4, 35, 0, 0x8010ULL, nullptr, nullptr, OperandInfo96, -1 ,nullptr }, // Inst #2928 = V6_vsubwsat
6581 { 2951, 3, 1, 4, 35, 0, 0x8010ULL, nullptr, nullptr, OperandInfo96, -1 ,nullptr }, // Inst #2951 = V6_vxor