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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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References
gen/lib/Target/Hexagon/HexagonGenInstrInfo.inc 4928 { 1298, 2, 0, 4, 124, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x7972801c04ULL, ImplicitList30, ImplicitList31, OperandInfo171, -1 ,nullptr }, // Inst #1298 = J4_tstbit0_fp0_jump_nt
4929 { 1299, 2, 0, 4, 124, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x2007972801c04ULL, ImplicitList30, ImplicitList31, OperandInfo171, -1 ,nullptr }, // Inst #1299 = J4_tstbit0_fp0_jump_t
4930 { 1300, 2, 0, 4, 124, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x7972801c04ULL, ImplicitList32, ImplicitList33, OperandInfo171, -1 ,nullptr }, // Inst #1300 = J4_tstbit0_fp1_jump_nt
4931 { 1301, 2, 0, 4, 124, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x2007972801c04ULL, ImplicitList32, ImplicitList33, OperandInfo171, -1 ,nullptr }, // Inst #1301 = J4_tstbit0_fp1_jump_t
4934 { 1304, 2, 0, 4, 124, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x7972801404ULL, ImplicitList30, ImplicitList31, OperandInfo171, -1 ,nullptr }, // Inst #1304 = J4_tstbit0_tp0_jump_nt
4935 { 1305, 2, 0, 4, 124, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x2007972801404ULL, ImplicitList30, ImplicitList31, OperandInfo171, -1 ,nullptr }, // Inst #1305 = J4_tstbit0_tp0_jump_t
4936 { 1306, 2, 0, 4, 124, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x7972801404ULL, ImplicitList32, ImplicitList33, OperandInfo171, -1 ,nullptr }, // Inst #1306 = J4_tstbit0_tp1_jump_nt
4937 { 1307, 2, 0, 4, 124, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x2007972801404ULL, ImplicitList32, ImplicitList33, OperandInfo171, -1 ,nullptr }, // Inst #1307 = J4_tstbit0_tp1_jump_t
5981 { 2351, 2, 1, 4, 173, 0, 0x802bULL, ImplicitList3, nullptr, OperandInfo171, -1 ,nullptr }, // Inst #2351 = SA1_addsp
5987 { 2357, 2, 0, 4, 176, 0, 0x2bULL, nullptr, ImplicitList30, OperandInfo171, -1 ,nullptr }, // Inst #2357 = SA1_cmpeqi
5996 { 2366, 2, 1, 4, 173, 0, 0xc280802bULL, nullptr, nullptr, OperandInfo171, -1 ,nullptr }, // Inst #2366 = SA1_seti
5997 { 2367, 2, 1, 4, 173, 0, 0x802bULL, nullptr, nullptr, OperandInfo171, -1 ,nullptr }, // Inst #2367 = SA1_setin1
6022 { 2392, 2, 1, 4, 127, 0|(1ULL<<MCID::MayLoad), 0x6c000000802bULL, ImplicitList3, nullptr, OperandInfo171, -1 ,nullptr }, // Inst #2392 = SL2_loadri_sp
6032 { 2402, 2, 0, 4, 181, 0|(1ULL<<MCID::MayStore), 0x2c000000002bULL, nullptr, nullptr, OperandInfo171, -1 ,nullptr }, // Inst #2402 = SS2_storebi0
6033 { 2403, 2, 0, 4, 181, 0|(1ULL<<MCID::MayStore), 0x2c000000002bULL, nullptr, nullptr, OperandInfo171, -1 ,nullptr }, // Inst #2403 = SS2_storebi1
6037 { 2407, 2, 0, 4, 181, 0|(1ULL<<MCID::MayStore), 0x6c000000002bULL, nullptr, nullptr, OperandInfo171, -1 ,nullptr }, // Inst #2407 = SS2_storewi0
6038 { 2408, 2, 0, 4, 181, 0|(1ULL<<MCID::MayStore), 0x6c000000002bULL, nullptr, nullptr, OperandInfo171, -1 ,nullptr }, // Inst #2408 = SS2_storewi1