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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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References
gen/lib/Target/Hexagon/HexagonGenInstrInfo.inc 4821 { 1191, 3, 0, 4, 118, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x7974801c04ULL, ImplicitList30, ImplicitList31, OperandInfo168, -1 ,nullptr }, // Inst #1191 = J4_cmpeq_fp0_jump_nt
4822 { 1192, 3, 0, 4, 118, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x2007974801c04ULL, ImplicitList30, ImplicitList31, OperandInfo168, -1 ,nullptr }, // Inst #1192 = J4_cmpeq_fp0_jump_t
4827 { 1197, 3, 0, 4, 118, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x7974801404ULL, ImplicitList30, ImplicitList31, OperandInfo168, -1 ,nullptr }, // Inst #1197 = J4_cmpeq_tp0_jump_nt
4828 { 1198, 3, 0, 4, 118, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x2007974801404ULL, ImplicitList30, ImplicitList31, OperandInfo168, -1 ,nullptr }, // Inst #1198 = J4_cmpeq_tp0_jump_t
4833 { 1203, 3, 0, 4, 120, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x7974801c04ULL, ImplicitList30, ImplicitList31, OperandInfo170, -1 ,nullptr }, // Inst #1203 = J4_cmpeqi_fp0_jump_nt
4834 { 1204, 3, 0, 4, 120, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x2007974801c04ULL, ImplicitList30, ImplicitList31, OperandInfo170, -1 ,nullptr }, // Inst #1204 = J4_cmpeqi_fp0_jump_t
4839 { 1209, 3, 0, 4, 120, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x7974801404ULL, ImplicitList30, ImplicitList31, OperandInfo170, -1 ,nullptr }, // Inst #1209 = J4_cmpeqi_tp0_jump_nt
4840 { 1210, 3, 0, 4, 120, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x2007974801404ULL, ImplicitList30, ImplicitList31, OperandInfo170, -1 ,nullptr }, // Inst #1210 = J4_cmpeqi_tp0_jump_t
4845 { 1215, 3, 0, 4, 120, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x7974801c04ULL, ImplicitList30, ImplicitList31, OperandInfo170, -1 ,nullptr }, // Inst #1215 = J4_cmpeqn1_fp0_jump_nt
4846 { 1216, 3, 0, 4, 120, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x2007974801c04ULL, ImplicitList30, ImplicitList31, OperandInfo170, -1 ,nullptr }, // Inst #1216 = J4_cmpeqn1_fp0_jump_t
4851 { 1221, 3, 0, 4, 120, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x7974801404ULL, ImplicitList30, ImplicitList31, OperandInfo170, -1 ,nullptr }, // Inst #1221 = J4_cmpeqn1_tp0_jump_nt
4852 { 1222, 3, 0, 4, 120, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x2007974801404ULL, ImplicitList30, ImplicitList31, OperandInfo170, -1 ,nullptr }, // Inst #1222 = J4_cmpeqn1_tp0_jump_t
4857 { 1227, 3, 0, 4, 118, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x7974801c04ULL, ImplicitList30, ImplicitList31, OperandInfo168, -1 ,nullptr }, // Inst #1227 = J4_cmpgt_fp0_jump_nt
4858 { 1228, 3, 0, 4, 118, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x2007974801c04ULL, ImplicitList30, ImplicitList31, OperandInfo168, -1 ,nullptr }, // Inst #1228 = J4_cmpgt_fp0_jump_t
4863 { 1233, 3, 0, 4, 118, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x7974801404ULL, ImplicitList30, ImplicitList31, OperandInfo168, -1 ,nullptr }, // Inst #1233 = J4_cmpgt_tp0_jump_nt
4864 { 1234, 3, 0, 4, 118, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x2007974801404ULL, ImplicitList30, ImplicitList31, OperandInfo168, -1 ,nullptr }, // Inst #1234 = J4_cmpgt_tp0_jump_t
4869 { 1239, 3, 0, 4, 120, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x7974801c04ULL, ImplicitList30, ImplicitList31, OperandInfo170, -1 ,nullptr }, // Inst #1239 = J4_cmpgti_fp0_jump_nt
4870 { 1240, 3, 0, 4, 120, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x2007974801c04ULL, ImplicitList30, ImplicitList31, OperandInfo170, -1 ,nullptr }, // Inst #1240 = J4_cmpgti_fp0_jump_t
4875 { 1245, 3, 0, 4, 120, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x7974801404ULL, ImplicitList30, ImplicitList31, OperandInfo170, -1 ,nullptr }, // Inst #1245 = J4_cmpgti_tp0_jump_nt
4876 { 1246, 3, 0, 4, 120, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x2007974801404ULL, ImplicitList30, ImplicitList31, OperandInfo170, -1 ,nullptr }, // Inst #1246 = J4_cmpgti_tp0_jump_t
4881 { 1251, 3, 0, 4, 120, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x7974801c04ULL, ImplicitList30, ImplicitList31, OperandInfo170, -1 ,nullptr }, // Inst #1251 = J4_cmpgtn1_fp0_jump_nt
4882 { 1252, 3, 0, 4, 120, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x2007974801c04ULL, ImplicitList30, ImplicitList31, OperandInfo170, -1 ,nullptr }, // Inst #1252 = J4_cmpgtn1_fp0_jump_t
4887 { 1257, 3, 0, 4, 120, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x7974801404ULL, ImplicitList30, ImplicitList31, OperandInfo170, -1 ,nullptr }, // Inst #1257 = J4_cmpgtn1_tp0_jump_nt
4888 { 1258, 3, 0, 4, 120, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x2007974801404ULL, ImplicitList30, ImplicitList31, OperandInfo170, -1 ,nullptr }, // Inst #1258 = J4_cmpgtn1_tp0_jump_t
4893 { 1263, 3, 0, 4, 118, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x7974801c04ULL, ImplicitList30, ImplicitList31, OperandInfo168, -1 ,nullptr }, // Inst #1263 = J4_cmpgtu_fp0_jump_nt
4894 { 1264, 3, 0, 4, 118, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x2007974801c04ULL, ImplicitList30, ImplicitList31, OperandInfo168, -1 ,nullptr }, // Inst #1264 = J4_cmpgtu_fp0_jump_t
4899 { 1269, 3, 0, 4, 118, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x7974801404ULL, ImplicitList30, ImplicitList31, OperandInfo168, -1 ,nullptr }, // Inst #1269 = J4_cmpgtu_tp0_jump_nt
4900 { 1270, 3, 0, 4, 118, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x2007974801404ULL, ImplicitList30, ImplicitList31, OperandInfo168, -1 ,nullptr }, // Inst #1270 = J4_cmpgtu_tp0_jump_t
4905 { 1275, 3, 0, 4, 120, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x7974801c04ULL, ImplicitList30, ImplicitList31, OperandInfo170, -1 ,nullptr }, // Inst #1275 = J4_cmpgtui_fp0_jump_nt
4906 { 1276, 3, 0, 4, 120, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x2007974801c04ULL, ImplicitList30, ImplicitList31, OperandInfo170, -1 ,nullptr }, // Inst #1276 = J4_cmpgtui_fp0_jump_t
4911 { 1281, 3, 0, 4, 120, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x7974801404ULL, ImplicitList30, ImplicitList31, OperandInfo170, -1 ,nullptr }, // Inst #1281 = J4_cmpgtui_tp0_jump_nt
4912 { 1282, 3, 0, 4, 120, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x2007974801404ULL, ImplicitList30, ImplicitList31, OperandInfo170, -1 ,nullptr }, // Inst #1282 = J4_cmpgtui_tp0_jump_t
4928 { 1298, 2, 0, 4, 124, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x7972801c04ULL, ImplicitList30, ImplicitList31, OperandInfo171, -1 ,nullptr }, // Inst #1298 = J4_tstbit0_fp0_jump_nt
4929 { 1299, 2, 0, 4, 124, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x2007972801c04ULL, ImplicitList30, ImplicitList31, OperandInfo171, -1 ,nullptr }, // Inst #1299 = J4_tstbit0_fp0_jump_t
4934 { 1304, 2, 0, 4, 124, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x7972801404ULL, ImplicitList30, ImplicitList31, OperandInfo171, -1 ,nullptr }, // Inst #1304 = J4_tstbit0_tp0_jump_nt
4935 { 1305, 2, 0, 4, 124, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x2007972801404ULL, ImplicitList30, ImplicitList31, OperandInfo171, -1 ,nullptr }, // Inst #1305 = J4_tstbit0_tp0_jump_t
5592 { 1962, 3, 1, 4, 148, 0, 0x20000000000202dULL, nullptr, ImplicitList30, OperandInfo43, -1 ,nullptr }, // Inst #1962 = S2_cabacdecbin
5983 { 2353, 1, 1, 4, 174, 0, 0x8c2bULL, ImplicitList30, nullptr, OperandInfo234, -1 ,nullptr }, // Inst #2353 = SA1_clrf
5984 { 2354, 1, 1, 4, 175, 0, 0x9c2bULL, ImplicitList30, nullptr, OperandInfo234, -1 ,nullptr }, // Inst #2354 = SA1_clrfnew
5985 { 2355, 1, 1, 4, 174, 0, 0x842bULL, ImplicitList30, nullptr, OperandInfo234, -1 ,nullptr }, // Inst #2355 = SA1_clrt
5986 { 2356, 1, 1, 4, 175, 0, 0x942bULL, ImplicitList30, nullptr, OperandInfo234, -1 ,nullptr }, // Inst #2356 = SA1_clrtnew
5987 { 2357, 2, 0, 4, 176, 0, 0x2bULL, nullptr, ImplicitList30, OperandInfo171, -1 ,nullptr }, // Inst #2357 = SA1_cmpeqi
6004 { 2374, 1, 0, 4, 33, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0xb10800024ULL, ImplicitList41, ImplicitList30, OperandInfo2, -1 ,nullptr }, // Inst #2374 = SAVE_REGISTERS_CALL_V4STK
6005 { 2375, 1, 0, 4, 33, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0xb11800024ULL, ImplicitList41, ImplicitList30, OperandInfo2, -1 ,nullptr }, // Inst #2375 = SAVE_REGISTERS_CALL_V4STK_EXT