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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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References
gen/lib/Target/Hexagon/HexagonGenInstrInfo.inc 3923 { 293, 6, 2, 4, 34, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x380000000025ULL, ImplicitList18, ImplicitList18, OperandInfo61, -1 ,nullptr }, // Inst #293 = PS_loadrb_pci
3923 { 293, 6, 2, 4, 34, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x380000000025ULL, ImplicitList18, ImplicitList18, OperandInfo61, -1 ,nullptr }, // Inst #293 = PS_loadrb_pci
3924 { 294, 5, 2, 4, 20, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x380000000025ULL, ImplicitList18, ImplicitList18, OperandInfo62, -1 ,nullptr }, // Inst #294 = PS_loadrb_pcr
3924 { 294, 5, 2, 4, 20, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x380000000025ULL, ImplicitList18, ImplicitList18, OperandInfo62, -1 ,nullptr }, // Inst #294 = PS_loadrb_pcr
3925 { 295, 6, 2, 4, 34, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x980000000025ULL, ImplicitList18, ImplicitList18, OperandInfo63, -1 ,nullptr }, // Inst #295 = PS_loadrd_pci
3925 { 295, 6, 2, 4, 34, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x980000000025ULL, ImplicitList18, ImplicitList18, OperandInfo63, -1 ,nullptr }, // Inst #295 = PS_loadrd_pci
3926 { 296, 5, 2, 4, 20, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x980000000025ULL, ImplicitList18, ImplicitList18, OperandInfo64, -1 ,nullptr }, // Inst #296 = PS_loadrd_pcr
3926 { 296, 5, 2, 4, 20, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x980000000025ULL, ImplicitList18, ImplicitList18, OperandInfo64, -1 ,nullptr }, // Inst #296 = PS_loadrd_pcr
3927 { 297, 6, 2, 4, 34, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x580000000025ULL, ImplicitList18, ImplicitList18, OperandInfo61, -1 ,nullptr }, // Inst #297 = PS_loadrh_pci
3927 { 297, 6, 2, 4, 34, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x580000000025ULL, ImplicitList18, ImplicitList18, OperandInfo61, -1 ,nullptr }, // Inst #297 = PS_loadrh_pci
3928 { 298, 5, 2, 4, 20, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x580000000025ULL, ImplicitList18, ImplicitList18, OperandInfo62, -1 ,nullptr }, // Inst #298 = PS_loadrh_pcr
3928 { 298, 5, 2, 4, 20, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x580000000025ULL, ImplicitList18, ImplicitList18, OperandInfo62, -1 ,nullptr }, // Inst #298 = PS_loadrh_pcr
3929 { 299, 6, 2, 4, 34, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x780000000025ULL, ImplicitList18, ImplicitList18, OperandInfo61, -1 ,nullptr }, // Inst #299 = PS_loadri_pci
3929 { 299, 6, 2, 4, 34, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x780000000025ULL, ImplicitList18, ImplicitList18, OperandInfo61, -1 ,nullptr }, // Inst #299 = PS_loadri_pci
3930 { 300, 5, 2, 4, 20, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x780000000025ULL, ImplicitList18, ImplicitList18, OperandInfo62, -1 ,nullptr }, // Inst #300 = PS_loadri_pcr
3930 { 300, 5, 2, 4, 20, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x780000000025ULL, ImplicitList18, ImplicitList18, OperandInfo62, -1 ,nullptr }, // Inst #300 = PS_loadri_pcr
3931 { 301, 6, 2, 4, 34, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x380000000025ULL, ImplicitList18, ImplicitList18, OperandInfo61, -1 ,nullptr }, // Inst #301 = PS_loadrub_pci
3931 { 301, 6, 2, 4, 34, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x380000000025ULL, ImplicitList18, ImplicitList18, OperandInfo61, -1 ,nullptr }, // Inst #301 = PS_loadrub_pci
3932 { 302, 5, 2, 4, 20, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x380000000025ULL, ImplicitList18, ImplicitList18, OperandInfo62, -1 ,nullptr }, // Inst #302 = PS_loadrub_pcr
3932 { 302, 5, 2, 4, 20, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x380000000025ULL, ImplicitList18, ImplicitList18, OperandInfo62, -1 ,nullptr }, // Inst #302 = PS_loadrub_pcr
3933 { 303, 6, 2, 4, 34, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x580000000025ULL, ImplicitList18, ImplicitList18, OperandInfo61, -1 ,nullptr }, // Inst #303 = PS_loadruh_pci
3933 { 303, 6, 2, 4, 34, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x580000000025ULL, ImplicitList18, ImplicitList18, OperandInfo61, -1 ,nullptr }, // Inst #303 = PS_loadruh_pci
3934 { 304, 5, 2, 4, 20, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x580000000025ULL, ImplicitList18, ImplicitList18, OperandInfo62, -1 ,nullptr }, // Inst #304 = PS_loadruh_pcr
3934 { 304, 5, 2, 4, 20, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x580000000025ULL, ImplicitList18, ImplicitList18, OperandInfo62, -1 ,nullptr }, // Inst #304 = PS_loadruh_pcr
3938 { 308, 6, 1, 4, 36, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x38000000002aULL, ImplicitList18, ImplicitList18, OperandInfo67, -1 ,nullptr }, // Inst #308 = PS_storerb_pci
3938 { 308, 6, 1, 4, 36, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x38000000002aULL, ImplicitList18, ImplicitList18, OperandInfo67, -1 ,nullptr }, // Inst #308 = PS_storerb_pci
3939 { 309, 5, 1, 4, 37, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x38000000002aULL, ImplicitList18, ImplicitList18, OperandInfo68, -1 ,nullptr }, // Inst #309 = PS_storerb_pcr
3939 { 309, 5, 1, 4, 37, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x38000000002aULL, ImplicitList18, ImplicitList18, OperandInfo68, -1 ,nullptr }, // Inst #309 = PS_storerb_pcr
3940 { 310, 6, 1, 4, 36, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x78000000002aULL, ImplicitList18, ImplicitList18, OperandInfo69, -1 ,nullptr }, // Inst #310 = PS_storerd_pci
3940 { 310, 6, 1, 4, 36, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x78000000002aULL, ImplicitList18, ImplicitList18, OperandInfo69, -1 ,nullptr }, // Inst #310 = PS_storerd_pci
3941 { 311, 5, 1, 4, 37, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x78000000002aULL, ImplicitList18, ImplicitList18, OperandInfo70, -1 ,nullptr }, // Inst #311 = PS_storerd_pcr
3941 { 311, 5, 1, 4, 37, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x78000000002aULL, ImplicitList18, ImplicitList18, OperandInfo70, -1 ,nullptr }, // Inst #311 = PS_storerd_pcr
3942 { 312, 6, 1, 4, 36, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x58000000002aULL, ImplicitList18, ImplicitList18, OperandInfo67, -1 ,nullptr }, // Inst #312 = PS_storerf_pci
3942 { 312, 6, 1, 4, 36, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x58000000002aULL, ImplicitList18, ImplicitList18, OperandInfo67, -1 ,nullptr }, // Inst #312 = PS_storerf_pci
3943 { 313, 5, 1, 4, 37, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x58000000002aULL, ImplicitList18, ImplicitList18, OperandInfo68, -1 ,nullptr }, // Inst #313 = PS_storerf_pcr
3943 { 313, 5, 1, 4, 37, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x58000000002aULL, ImplicitList18, ImplicitList18, OperandInfo68, -1 ,nullptr }, // Inst #313 = PS_storerf_pcr
3944 { 314, 6, 1, 4, 36, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x58000000002aULL, ImplicitList18, ImplicitList18, OperandInfo67, -1 ,nullptr }, // Inst #314 = PS_storerh_pci
3944 { 314, 6, 1, 4, 36, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x58000000002aULL, ImplicitList18, ImplicitList18, OperandInfo67, -1 ,nullptr }, // Inst #314 = PS_storerh_pci
3945 { 315, 5, 1, 4, 37, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x58000000002aULL, ImplicitList18, ImplicitList18, OperandInfo68, -1 ,nullptr }, // Inst #315 = PS_storerh_pcr
3945 { 315, 5, 1, 4, 37, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x58000000002aULL, ImplicitList18, ImplicitList18, OperandInfo68, -1 ,nullptr }, // Inst #315 = PS_storerh_pcr
3946 { 316, 6, 1, 4, 36, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x78000000002aULL, ImplicitList18, ImplicitList18, OperandInfo67, -1 ,nullptr }, // Inst #316 = PS_storeri_pci
3946 { 316, 6, 1, 4, 36, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x78000000002aULL, ImplicitList18, ImplicitList18, OperandInfo67, -1 ,nullptr }, // Inst #316 = PS_storeri_pci
3947 { 317, 5, 1, 4, 37, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x78000000002aULL, ImplicitList18, ImplicitList18, OperandInfo68, -1 ,nullptr }, // Inst #317 = PS_storeri_pcr
3947 { 317, 5, 1, 4, 37, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x78000000002aULL, ImplicitList18, ImplicitList18, OperandInfo68, -1 ,nullptr }, // Inst #317 = PS_storeri_pcr
4941 { 1311, 6, 2, 4, 126, 0|(1ULL<<MCID::MayLoad), 0x380000000025ULL, ImplicitList18, nullptr, OperandInfo174, -1 ,nullptr }, // Inst #1311 = L2_loadalignb_pci
4942 { 1312, 5, 2, 4, 125, 0|(1ULL<<MCID::MayLoad), 0x380000000025ULL, ImplicitList18, nullptr, OperandInfo173, -1 ,nullptr }, // Inst #1312 = L2_loadalignb_pcr
4947 { 1317, 6, 2, 4, 126, 0|(1ULL<<MCID::MayLoad), 0x580000000025ULL, ImplicitList18, nullptr, OperandInfo174, -1 ,nullptr }, // Inst #1317 = L2_loadalignh_pci
4948 { 1318, 5, 2, 4, 125, 0|(1ULL<<MCID::MayLoad), 0x580000000025ULL, ImplicitList18, nullptr, OperandInfo173, -1 ,nullptr }, // Inst #1318 = L2_loadalignh_pcr
4953 { 1323, 5, 2, 4, 34, 0|(1ULL<<MCID::MayLoad), 0x580000008025ULL, ImplicitList18, nullptr, OperandInfo177, -1 ,nullptr }, // Inst #1323 = L2_loadbsw2_pci
4954 { 1324, 4, 2, 4, 20, 0|(1ULL<<MCID::MayLoad), 0x580000008025ULL, ImplicitList18, nullptr, OperandInfo176, -1 ,nullptr }, // Inst #1324 = L2_loadbsw2_pcr
4959 { 1329, 5, 2, 4, 34, 0|(1ULL<<MCID::MayLoad), 0x780000000025ULL, ImplicitList18, nullptr, OperandInfo180, -1 ,nullptr }, // Inst #1329 = L2_loadbsw4_pci
4960 { 1330, 4, 2, 4, 20, 0|(1ULL<<MCID::MayLoad), 0x780000000025ULL, ImplicitList18, nullptr, OperandInfo179, -1 ,nullptr }, // Inst #1330 = L2_loadbsw4_pcr
4965 { 1335, 5, 2, 4, 34, 0|(1ULL<<MCID::MayLoad), 0x580000008025ULL, ImplicitList18, nullptr, OperandInfo177, -1 ,nullptr }, // Inst #1335 = L2_loadbzw2_pci
4966 { 1336, 4, 2, 4, 20, 0|(1ULL<<MCID::MayLoad), 0x580000008025ULL, ImplicitList18, nullptr, OperandInfo176, -1 ,nullptr }, // Inst #1336 = L2_loadbzw2_pcr
4971 { 1341, 5, 2, 4, 34, 0|(1ULL<<MCID::MayLoad), 0x780000000025ULL, ImplicitList18, nullptr, OperandInfo180, -1 ,nullptr }, // Inst #1341 = L2_loadbzw4_pci
4972 { 1342, 4, 2, 4, 20, 0|(1ULL<<MCID::MayLoad), 0x780000000025ULL, ImplicitList18, nullptr, OperandInfo179, -1 ,nullptr }, // Inst #1342 = L2_loadbzw4_pcr
4977 { 1347, 5, 2, 4, 34, 0|(1ULL<<MCID::MayLoad), 0x380000008025ULL, ImplicitList18, nullptr, OperandInfo177, -1 ,nullptr }, // Inst #1347 = L2_loadrb_pci
4978 { 1348, 4, 2, 4, 20, 0|(1ULL<<MCID::MayLoad), 0x380000008025ULL, ImplicitList18, nullptr, OperandInfo176, -1 ,nullptr }, // Inst #1348 = L2_loadrb_pcr
4984 { 1354, 5, 2, 4, 34, 0|(1ULL<<MCID::MayLoad), 0x980000000025ULL, ImplicitList18, nullptr, OperandInfo180, -1 ,nullptr }, // Inst #1354 = L2_loadrd_pci
4985 { 1355, 4, 2, 4, 20, 0|(1ULL<<MCID::MayLoad), 0x980000000025ULL, ImplicitList18, nullptr, OperandInfo179, -1 ,nullptr }, // Inst #1355 = L2_loadrd_pcr
4991 { 1361, 5, 2, 4, 34, 0|(1ULL<<MCID::MayLoad), 0x580000008025ULL, ImplicitList18, nullptr, OperandInfo177, -1 ,nullptr }, // Inst #1361 = L2_loadrh_pci
4992 { 1362, 4, 2, 4, 20, 0|(1ULL<<MCID::MayLoad), 0x580000008025ULL, ImplicitList18, nullptr, OperandInfo176, -1 ,nullptr }, // Inst #1362 = L2_loadrh_pcr
4998 { 1368, 5, 2, 4, 34, 0|(1ULL<<MCID::MayLoad), 0x780000008025ULL, ImplicitList18, nullptr, OperandInfo177, -1 ,nullptr }, // Inst #1368 = L2_loadri_pci
4999 { 1369, 4, 2, 4, 20, 0|(1ULL<<MCID::MayLoad), 0x780000008025ULL, ImplicitList18, nullptr, OperandInfo176, -1 ,nullptr }, // Inst #1369 = L2_loadri_pcr
5005 { 1375, 5, 2, 4, 34, 0|(1ULL<<MCID::MayLoad), 0x380000008025ULL, ImplicitList18, nullptr, OperandInfo177, -1 ,nullptr }, // Inst #1375 = L2_loadrub_pci
5006 { 1376, 4, 2, 4, 20, 0|(1ULL<<MCID::MayLoad), 0x380000008025ULL, ImplicitList18, nullptr, OperandInfo176, -1 ,nullptr }, // Inst #1376 = L2_loadrub_pcr
5012 { 1382, 5, 2, 4, 34, 0|(1ULL<<MCID::MayLoad), 0x580000008025ULL, ImplicitList18, nullptr, OperandInfo177, -1 ,nullptr }, // Inst #1382 = L2_loadruh_pci
5013 { 1383, 4, 2, 4, 20, 0|(1ULL<<MCID::MayLoad), 0x580000008025ULL, ImplicitList18, nullptr, OperandInfo176, -1 ,nullptr }, // Inst #1383 = L2_loadruh_pcr
5716 { 2086, 5, 1, 4, 36, 0|(1ULL<<MCID::MayStore), 0x38000008002aULL, ImplicitList18, nullptr, OperandInfo211, -1 ,nullptr }, // Inst #2086 = S2_storerb_pci
5717 { 2087, 4, 1, 4, 37, 0|(1ULL<<MCID::MayStore), 0x38000008002aULL, ImplicitList18, nullptr, OperandInfo210, -1 ,nullptr }, // Inst #2087 = S2_storerb_pcr
5723 { 2093, 5, 1, 4, 153, 0|(1ULL<<MCID::MayStore), 0x38800014402aULL, ImplicitList18, nullptr, OperandInfo211, -1 ,nullptr }, // Inst #2093 = S2_storerbnew_pci
5724 { 2094, 4, 1, 4, 53, 0|(1ULL<<MCID::MayStore), 0x38800013402aULL, ImplicitList18, nullptr, OperandInfo210, -1 ,nullptr }, // Inst #2094 = S2_storerbnew_pcr
5730 { 2100, 5, 1, 4, 36, 0|(1ULL<<MCID::MayStore), 0x98000000002aULL, ImplicitList18, nullptr, OperandInfo215, -1 ,nullptr }, // Inst #2100 = S2_storerd_pci
5731 { 2101, 4, 1, 4, 37, 0|(1ULL<<MCID::MayStore), 0x98000000002aULL, ImplicitList18, nullptr, OperandInfo214, -1 ,nullptr }, // Inst #2101 = S2_storerd_pcr
5737 { 2107, 5, 1, 4, 36, 0|(1ULL<<MCID::MayStore), 0x58000000002aULL, ImplicitList18, nullptr, OperandInfo211, -1 ,nullptr }, // Inst #2107 = S2_storerf_pci
5738 { 2108, 4, 1, 4, 37, 0|(1ULL<<MCID::MayStore), 0x58000000002aULL, ImplicitList18, nullptr, OperandInfo210, -1 ,nullptr }, // Inst #2108 = S2_storerf_pcr
5744 { 2114, 5, 1, 4, 36, 0|(1ULL<<MCID::MayStore), 0x58000008002aULL, ImplicitList18, nullptr, OperandInfo211, -1 ,nullptr }, // Inst #2114 = S2_storerh_pci
5745 { 2115, 4, 1, 4, 37, 0|(1ULL<<MCID::MayStore), 0x58000008002aULL, ImplicitList18, nullptr, OperandInfo210, -1 ,nullptr }, // Inst #2115 = S2_storerh_pcr
5751 { 2121, 5, 1, 4, 153, 0|(1ULL<<MCID::MayStore), 0x58800014402aULL, ImplicitList18, nullptr, OperandInfo211, -1 ,nullptr }, // Inst #2121 = S2_storerhnew_pci
5752 { 2122, 4, 1, 4, 53, 0|(1ULL<<MCID::MayStore), 0x58800013402aULL, ImplicitList18, nullptr, OperandInfo210, -1 ,nullptr }, // Inst #2122 = S2_storerhnew_pcr
5758 { 2128, 5, 1, 4, 36, 0|(1ULL<<MCID::MayStore), 0x78000008002aULL, ImplicitList18, nullptr, OperandInfo211, -1 ,nullptr }, // Inst #2128 = S2_storeri_pci
5759 { 2129, 4, 1, 4, 37, 0|(1ULL<<MCID::MayStore), 0x78000008002aULL, ImplicitList18, nullptr, OperandInfo210, -1 ,nullptr }, // Inst #2129 = S2_storeri_pcr
5765 { 2135, 5, 1, 4, 153, 0|(1ULL<<MCID::MayStore), 0x78800014402aULL, ImplicitList18, nullptr, OperandInfo211, -1 ,nullptr }, // Inst #2135 = S2_storerinew_pci
5766 { 2136, 4, 1, 4, 53, 0|(1ULL<<MCID::MayStore), 0x78800013402aULL, ImplicitList18, nullptr, OperandInfo210, -1 ,nullptr }, // Inst #2136 = S2_storerinew_pcr