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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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References
gen/lib/Target/Hexagon/HexagonGenAsmMatcher.inc 5575 return MCK_vmpyweuh; // "vmpyweuh"
7215 case MCK_vmpyweuh: return "MCK_vmpyweuh";
8317 { 0 /* */, Hexagon::M2_mmpyul_s0, Convert__Reg1_0__Reg1_4__Reg1_5, AMFBS_None, { MCK_DoubleRegs, MCK__61_, MCK_vmpyweuh, MCK__40_, MCK_DoubleRegs, MCK_DoubleRegs, MCK__41_, MCK__COLON_, MCK_sat }, },
8499 { 0 /* */, Hexagon::M2_mmaculs_s0, Convert__Reg1_0__Tie0_0_0__Reg1_5__Reg1_6, AMFBS_None, { MCK_DoubleRegs, MCK__43_, MCK__61_, MCK_vmpyweuh, MCK__40_, MCK_DoubleRegs, MCK_DoubleRegs, MCK__41_, MCK__COLON_, MCK_sat }, },
8605 { 0 /* */, Hexagon::M2_mmpyul_rs0, Convert__Reg1_0__Reg1_4__Reg1_5, AMFBS_None, { MCK_DoubleRegs, MCK__61_, MCK_vmpyweuh, MCK__40_, MCK_DoubleRegs, MCK_DoubleRegs, MCK__41_, MCK__COLON_, MCK_rnd, MCK__COLON_, MCK_sat }, },
8679 { 0 /* */, Hexagon::M2_mmaculs_rs0, Convert__Reg1_0__Tie0_0_0__Reg1_5__Reg1_6, AMFBS_None, { MCK_DoubleRegs, MCK__43_, MCK__61_, MCK_vmpyweuh, MCK__40_, MCK_DoubleRegs, MCK_DoubleRegs, MCK__41_, MCK__COLON_, MCK_rnd, MCK__COLON_, MCK_sat }, },
8779 { 0 /* */, Hexagon::M2_mmpyul_s1, Convert__Reg1_0__Reg1_4__Reg1_5, AMFBS_None, { MCK_DoubleRegs, MCK__61_, MCK_vmpyweuh, MCK__40_, MCK_DoubleRegs, MCK_DoubleRegs, MCK__41_, MCK__COLON_, MCK__LT_, MCK__LT_, MCK_1, MCK__COLON_, MCK_sat }, },
8976 { 0 /* */, Hexagon::M2_mmaculs_s1, Convert__Reg1_0__Tie0_0_0__Reg1_5__Reg1_6, AMFBS_None, { MCK_DoubleRegs, MCK__43_, MCK__61_, MCK_vmpyweuh, MCK__40_, MCK_DoubleRegs, MCK_DoubleRegs, MCK__41_, MCK__COLON_, MCK__LT_, MCK__LT_, MCK_1, MCK__COLON_, MCK_sat }, },
9074 { 0 /* */, Hexagon::M2_mmpyul_rs1, Convert__Reg1_0__Reg1_4__Reg1_5, AMFBS_None, { MCK_DoubleRegs, MCK__61_, MCK_vmpyweuh, MCK__40_, MCK_DoubleRegs, MCK_DoubleRegs, MCK__41_, MCK__COLON_, MCK__LT_, MCK__LT_, MCK_1, MCK__COLON_, MCK_rnd, MCK__COLON_, MCK_sat }, },
9185 { 0 /* */, Hexagon::M2_mmaculs_rs1, Convert__Reg1_0__Tie0_0_0__Reg1_5__Reg1_6, AMFBS_None, { MCK_DoubleRegs, MCK__43_, MCK__61_, MCK_vmpyweuh, MCK__40_, MCK_DoubleRegs, MCK_DoubleRegs, MCK__41_, MCK__COLON_, MCK__LT_, MCK__LT_, MCK_1, MCK__COLON_, MCK_rnd, MCK__COLON_, MCK_sat }, },