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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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References
gen/lib/Target/Hexagon/HexagonGenAsmMatcher.inc 4306 return MCK_vmpyh; // "vmpyh"
7195 case MCK_vmpyh: return "MCK_vmpyh";
7863 { 0 /* */, Hexagon::V6_vmpyh, Convert__Reg1_0__Reg1_4__Reg1_5, AMFBS_UseHVX, { MCK_HvxWR, MCK__61_, MCK_vmpyh, MCK__40_, MCK_HvxVR, MCK_IntRegs, MCK__41_ }, },
7864 { 0 /* */, Hexagon::V6_vmpyhv, Convert__Reg1_0__Reg1_4__Reg1_5, AMFBS_UseHVX, { MCK_HvxWR, MCK__61_, MCK_vmpyh, MCK__40_, MCK_HvxVR, MCK_HvxVR, MCK__41_ }, },
8042 { 0 /* */, Hexagon::M2_vmac2, Convert__Reg1_0__Tie0_0_0__Reg1_5__Reg1_6, AMFBS_None, { MCK_DoubleRegs, MCK__43_, MCK__61_, MCK_vmpyh, MCK__40_, MCK_IntRegs, MCK_IntRegs, MCK__41_ }, },
8115 { 0 /* */, Hexagon::V6_vmpyh_acc, Convert__Reg1_0__Tie0_0_0__Reg1_5__Reg1_6, AMFBS_UseHVX, { MCK_HvxWR, MCK__43_, MCK__61_, MCK_vmpyh, MCK__40_, MCK_HvxVR, MCK_IntRegs, MCK__41_ }, },
8116 { 0 /* */, Hexagon::V6_vmpyhv_acc, Convert__Reg1_0__Tie0_0_0__Reg1_5__Reg1_6, AMFBS_UseHVX, { MCK_HvxWR, MCK__43_, MCK__61_, MCK_vmpyh, MCK__40_, MCK_HvxVR, MCK_HvxVR, MCK__41_ }, },
8314 { 0 /* */, Hexagon::M2_vmpy2s_s0, Convert__Reg1_0__Reg1_4__Reg1_5, AMFBS_None, { MCK_DoubleRegs, MCK__61_, MCK_vmpyh, MCK__40_, MCK_IntRegs, MCK_IntRegs, MCK__41_, MCK__COLON_, MCK_sat }, },
8496 { 0 /* */, Hexagon::M2_vmac2s_s0, Convert__Reg1_0__Tie0_0_0__Reg1_5__Reg1_6, AMFBS_None, { MCK_DoubleRegs, MCK__43_, MCK__61_, MCK_vmpyh, MCK__40_, MCK_IntRegs, MCK_IntRegs, MCK__41_, MCK__COLON_, MCK_sat }, },
8518 { 0 /* */, Hexagon::V6_vmpyhsat_acc, Convert__Reg1_0__Tie0_0_0__Reg1_5__Reg1_6, AMFBS_UseHVX, { MCK_HvxWR, MCK__43_, MCK__61_, MCK_vmpyh, MCK__40_, MCK_HvxVR, MCK_IntRegs, MCK__41_, MCK__COLON_, MCK_sat }, },
8650 { 0 /* */, Hexagon::M2_vmpy2s_s0pack, Convert__Reg1_0__Reg1_4__Reg1_5, AMFBS_None, { MCK_IntRegs, MCK__61_, MCK_vmpyh, MCK__40_, MCK_IntRegs, MCK_IntRegs, MCK__41_, MCK__COLON_, MCK_rnd, MCK__COLON_, MCK_sat }, },
8776 { 0 /* */, Hexagon::M2_vmpy2s_s1, Convert__Reg1_0__Reg1_4__Reg1_5, AMFBS_None, { MCK_DoubleRegs, MCK__61_, MCK_vmpyh, MCK__40_, MCK_IntRegs, MCK_IntRegs, MCK__41_, MCK__COLON_, MCK__LT_, MCK__LT_, MCK_1, MCK__COLON_, MCK_sat }, },
8926 { 0 /* */, Hexagon::V6_vmpyhss, Convert__Reg1_0__Reg1_4__Reg1_5, AMFBS_UseHVX, { MCK_HvxVR, MCK__61_, MCK_vmpyh, MCK__40_, MCK_HvxVR, MCK_IntRegs, MCK__41_, MCK__COLON_, MCK__LT_, MCK__LT_, MCK_1, MCK__COLON_, MCK_sat }, },
8973 { 0 /* */, Hexagon::M2_vmac2s_s1, Convert__Reg1_0__Tie0_0_0__Reg1_5__Reg1_6, AMFBS_None, { MCK_DoubleRegs, MCK__43_, MCK__61_, MCK_vmpyh, MCK__40_, MCK_IntRegs, MCK_IntRegs, MCK__41_, MCK__COLON_, MCK__LT_, MCK__LT_, MCK_1, MCK__COLON_, MCK_sat }, },
9129 { 0 /* */, Hexagon::M2_vmpy2s_s1pack, Convert__Reg1_0__Reg1_4__Reg1_5, AMFBS_None, { MCK_IntRegs, MCK__61_, MCK_vmpyh, MCK__40_, MCK_IntRegs, MCK_IntRegs, MCK__41_, MCK__COLON_, MCK__LT_, MCK__LT_, MCK_1, MCK__COLON_, MCK_rnd, MCK__COLON_, MCK_sat }, },
9168 { 0 /* */, Hexagon::V6_vmpyhsrs, Convert__Reg1_0__Reg1_4__Reg1_5, AMFBS_UseHVX, { MCK_HvxVR, MCK__61_, MCK_vmpyh, MCK__40_, MCK_HvxVR, MCK_IntRegs, MCK__41_, MCK__COLON_, MCK__LT_, MCK__LT_, MCK_1, MCK__COLON_, MCK_rnd, MCK__COLON_, MCK_sat }, },
9169 { 0 /* */, Hexagon::V6_vmpyhvsrs, Convert__Reg1_0__Reg1_4__Reg1_5, AMFBS_UseHVX, { MCK_HvxVR, MCK__61_, MCK_vmpyh, MCK__40_, MCK_HvxVR, MCK_HvxVR, MCK__41_, MCK__COLON_, MCK__LT_, MCK__LT_, MCK_1, MCK__COLON_, MCK_rnd, MCK__COLON_, MCK_sat }, },