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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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References
gen/lib/Target/Hexagon/HexagonGenAsmMatcher.inc 3829 return MCK_vmpa; // "vmpa"
7181 case MCK_vmpa: return "MCK_vmpa";
8789 { 0 /* */, Hexagon::V6_vmpabusv, Convert__Reg1_0__Reg1_6__Reg1_9, AMFBS_UseHVXV60, { MCK_HvxWR, MCK__DOT_, MCK_h, MCK__61_, MCK_vmpa, MCK__40_, MCK_HvxWR, MCK__DOT_, MCK_ub, MCK_HvxWR, MCK__DOT_, MCK_b, MCK__41_ }, },
8790 { 0 /* */, Hexagon::V6_vmpabuuv, Convert__Reg1_0__Reg1_6__Reg1_9, AMFBS_UseHVXV60, { MCK_HvxWR, MCK__DOT_, MCK_h, MCK__61_, MCK_vmpa, MCK__40_, MCK_HvxWR, MCK__DOT_, MCK_ub, MCK_HvxWR, MCK__DOT_, MCK_ub, MCK__41_ }, },
8791 { 0 /* */, Hexagon::V6_vmpabus, Convert__Reg1_0__Reg1_6__Reg1_9, AMFBS_UseHVXV60, { MCK_HvxWR, MCK__DOT_, MCK_h, MCK__61_, MCK_vmpa, MCK__40_, MCK_HvxWR, MCK__DOT_, MCK_ub, MCK_IntRegs, MCK__DOT_, MCK_b, MCK__41_ }, },
8792 { 0 /* */, Hexagon::V6_vmpabuu, Convert__Reg1_0__Reg1_6__Reg1_9, AMFBS_UseHVXV65, { MCK_HvxWR, MCK__DOT_, MCK_h, MCK__61_, MCK_vmpa, MCK__40_, MCK_HvxWR, MCK__DOT_, MCK_ub, MCK_IntRegs, MCK__DOT_, MCK_ub, MCK__41_ }, },
8813 { 0 /* */, Hexagon::V6_vmpahb, Convert__Reg1_0__Reg1_6__Reg1_9, AMFBS_UseHVXV60, { MCK_HvxWR, MCK__DOT_, MCK_w, MCK__61_, MCK_vmpa, MCK__40_, MCK_HvxWR, MCK__DOT_, MCK_h, MCK_IntRegs, MCK__DOT_, MCK_b, MCK__41_ }, },
8814 { 0 /* */, Hexagon::V6_vmpauhb, Convert__Reg1_0__Reg1_6__Reg1_9, AMFBS_UseHVXV62, { MCK_HvxWR, MCK__DOT_, MCK_w, MCK__61_, MCK_vmpa, MCK__40_, MCK_HvxWR, MCK__DOT_, MCK_uh, MCK_IntRegs, MCK__DOT_, MCK_b, MCK__41_ }, },
8989 { 0 /* */, Hexagon::V6_vmpabus_acc, Convert__Reg1_0__Tie0_0_0__Reg1_7__Reg1_10, AMFBS_UseHVXV60, { MCK_HvxWR, MCK__DOT_, MCK_h, MCK__43_, MCK__61_, MCK_vmpa, MCK__40_, MCK_HvxWR, MCK__DOT_, MCK_ub, MCK_IntRegs, MCK__DOT_, MCK_b, MCK__41_ }, },
8990 { 0 /* */, Hexagon::V6_vmpabuu_acc, Convert__Reg1_0__Tie0_0_0__Reg1_7__Reg1_10, AMFBS_UseHVXV65, { MCK_HvxWR, MCK__DOT_, MCK_h, MCK__43_, MCK__61_, MCK_vmpa, MCK__40_, MCK_HvxWR, MCK__DOT_, MCK_ub, MCK_IntRegs, MCK__DOT_, MCK_ub, MCK__41_ }, },
9007 { 0 /* */, Hexagon::V6_vmpahb_acc, Convert__Reg1_0__Tie0_0_0__Reg1_7__Reg1_10, AMFBS_UseHVXV60, { MCK_HvxWR, MCK__DOT_, MCK_w, MCK__43_, MCK__61_, MCK_vmpa, MCK__40_, MCK_HvxWR, MCK__DOT_, MCK_h, MCK_IntRegs, MCK__DOT_, MCK_b, MCK__41_ }, },
9008 { 0 /* */, Hexagon::V6_vmpauhb_acc, Convert__Reg1_0__Tie0_0_0__Reg1_7__Reg1_10, AMFBS_UseHVXV62, { MCK_HvxWR, MCK__DOT_, MCK_w, MCK__43_, MCK__61_, MCK_vmpa, MCK__40_, MCK_HvxWR, MCK__DOT_, MCK_uh, MCK_IntRegs, MCK__DOT_, MCK_b, MCK__41_ }, },
9278 { 0 /* */, Hexagon::V6_vmpahhsat, Convert__Reg1_0__Tie0_0_6__Reg1_9__Reg1_12, AMFBS_UseHVXV65, { MCK_HvxVR, MCK__DOT_, MCK_h, MCK__61_, MCK_vmpa, MCK__40_, MCK_HvxVR, MCK__DOT_, MCK_h, MCK_HvxVR, MCK__DOT_, MCK_h, MCK_DoubleRegs, MCK__DOT_, MCK_h, MCK__41_, MCK__COLON_, MCK_sat }, },
9279 { 0 /* */, Hexagon::V6_vmpauhuhsat, Convert__Reg1_0__Tie0_0_6__Reg1_9__Reg1_12, AMFBS_UseHVXV65, { MCK_HvxVR, MCK__DOT_, MCK_h, MCK__61_, MCK_vmpa, MCK__40_, MCK_HvxVR, MCK__DOT_, MCK_h, MCK_HvxVR, MCK__DOT_, MCK_uh, MCK_DoubleRegs, MCK__DOT_, MCK_uh, MCK__41_, MCK__COLON_, MCK_sat }, },