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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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References
gen/lib/Target/Hexagon/HexagonGenAsmMatcher.inc 3772 return MCK_vand; // "vand"
7104 case MCK_vand: return "MCK_vand";
7731 { 0 /* */, Hexagon::V6_vandvrt, Convert__Reg1_0__Reg1_4__Reg1_5, AMFBS_UseHVXV60, { MCK_HvxQR, MCK__61_, MCK_vand, MCK__40_, MCK_HvxVR, MCK_IntRegs, MCK__41_ }, },
7943 { 0 /* */, Hexagon::V6_vandqrt, Convert__Reg1_0__Reg1_4__Reg1_5, AMFBS_UseHVXV60, { MCK_HvxVR, MCK__61_, MCK_vand, MCK__40_, MCK_HvxQR, MCK_IntRegs, MCK__41_ }, },
7944 { 0 /* */, Hexagon::V6_vandvqv, Convert__Reg1_0__Reg1_4__Reg1_5, AMFBS_UseHVXV62, { MCK_HvxVR, MCK__61_, MCK_vand, MCK__40_, MCK_HvxQR, MCK_HvxVR, MCK__41_ }, },
7945 { 0 /* */, Hexagon::V6_vand, Convert__Reg1_0__Reg1_4__Reg1_5, AMFBS_UseHVXV60, { MCK_HvxVR, MCK__61_, MCK_vand, MCK__40_, MCK_HvxVR, MCK_HvxVR, MCK__41_ }, },
8016 { 0 /* */, Hexagon::V6_vandvrt_acc, Convert__Reg1_0__Tie0_0_0__Reg1_5__Reg1_6, AMFBS_UseHVXV60, { MCK_HvxQR, MCK__124_, MCK__61_, MCK_vand, MCK__40_, MCK_HvxVR, MCK_IntRegs, MCK__41_ }, },
8218 { 0 /* */, Hexagon::V6_vandnqrt, Convert__Reg1_0__Reg1_5__Reg1_6, AMFBS_UseHVXV62, { MCK_HvxVR, MCK__61_, MCK_vand, MCK__40_, MCK__EXCLAIM_, MCK_HvxQR, MCK_IntRegs, MCK__41_ }, },
8219 { 0 /* */, Hexagon::V6_vandvnqv, Convert__Reg1_0__Reg1_5__Reg1_6, AMFBS_UseHVXV62, { MCK_HvxVR, MCK__61_, MCK_vand, MCK__40_, MCK__EXCLAIM_, MCK_HvxQR, MCK_HvxVR, MCK__41_ }, },
8225 { 0 /* */, Hexagon::V6_vandqrt_acc, Convert__Reg1_0__Tie0_0_0__Reg1_5__Reg1_6, AMFBS_UseHVXV60, { MCK_HvxVR, MCK__124_, MCK__61_, MCK_vand, MCK__40_, MCK_HvxQR, MCK_IntRegs, MCK__41_ }, },
8466 { 0 /* */, Hexagon::V6_vandnqrt_acc, Convert__Reg1_0__Tie0_0_0__Reg1_6__Reg1_7, AMFBS_UseHVXV62, { MCK_HvxVR, MCK__124_, MCK__61_, MCK_vand, MCK__40_, MCK__EXCLAIM_, MCK_HvxQR, MCK_IntRegs, MCK__41_ }, },
8743 { 0 /* */, Hexagon::V6_vandvrt, Convert__Reg1_0__Reg1_6__Reg1_9, AMFBS_UseHVX, { MCK_HvxQR, MCK__DOT_, MCK_ub, MCK__61_, MCK_vand, MCK__40_, MCK_HvxVR, MCK__DOT_, MCK_ub, MCK_IntRegs, MCK__DOT_, MCK_ub, MCK__41_ }, },
8888 { 0 /* */, Hexagon::V6_vandqrt, Convert__Reg1_0__Reg1_6__Reg1_9, AMFBS_UseHVX, { MCK_HvxVR, MCK__DOT_, MCK_ub, MCK__61_, MCK_vand, MCK__40_, MCK_HvxQR, MCK__DOT_, MCK_ub, MCK_IntRegs, MCK__DOT_, MCK_ub, MCK__41_ }, },
8940 { 0 /* */, Hexagon::V6_vandvrt_acc, Convert__Reg1_0__Tie0_0_0__Reg1_7__Reg1_10, AMFBS_UseHVX, { MCK_HvxQR, MCK__DOT_, MCK_ub, MCK__124_, MCK__61_, MCK_vand, MCK__40_, MCK_HvxVR, MCK__DOT_, MCK_ub, MCK_IntRegs, MCK__DOT_, MCK_ub, MCK__41_ }, },
9039 { 0 /* */, Hexagon::V6_vandnqrt, Convert__Reg1_0__Reg1_7__Reg1_10, AMFBS_UseHVX, { MCK_HvxVR, MCK__DOT_, MCK_ub, MCK__61_, MCK_vand, MCK__40_, MCK__EXCLAIM_, MCK_HvxQR, MCK__DOT_, MCK_ub, MCK_IntRegs, MCK__DOT_, MCK_ub, MCK__41_ }, },
9040 { 0 /* */, Hexagon::V6_vandqrt_acc, Convert__Reg1_0__Tie0_0_0__Reg1_7__Reg1_10, AMFBS_UseHVX, { MCK_HvxVR, MCK__DOT_, MCK_ub, MCK__124_, MCK__61_, MCK_vand, MCK__40_, MCK_HvxQR, MCK__DOT_, MCK_ub, MCK_IntRegs, MCK__DOT_, MCK_ub, MCK__41_ }, },
9151 { 0 /* */, Hexagon::V6_vandnqrt_acc, Convert__Reg1_0__Tie0_0_0__Reg1_8__Reg1_11, AMFBS_UseHVX, { MCK_HvxVR, MCK__DOT_, MCK_ub, MCK__124_, MCK__61_, MCK_vand, MCK__40_, MCK__EXCLAIM_, MCK_HvxQR, MCK__DOT_, MCK_ub, MCK_IntRegs, MCK__DOT_, MCK_ub, MCK__41_ }, },