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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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References
gen/lib/Target/Hexagon/HexagonGenAsmMatcher.inc 3592 return MCK_tmp; // "tmp"
7073 case MCK_tmp: return "MCK_tmp";
8655 { 0 /* */, Hexagon::V6_vL32b_tmp_ai, Convert__Reg1_0__Reg1_6__s4_0Imm1_9, AMFBS_UseHVXV60, { MCK_HvxVR, MCK__DOT_, MCK_tmp, MCK__61_, MCK_vmem, MCK__40_, MCK_IntRegs, MCK__43_, MCK__HASH_, MCK_s4_0Imm, MCK__41_ }, },
8656 { 0 /* */, Hexagon::V6_vL32b_tmp_ppu, Convert__Reg1_0__Reg1_6__Tie1_0_0__Reg1_9, AMFBS_UseHVXV60, { MCK_HvxVR, MCK__DOT_, MCK_tmp, MCK__61_, MCK_vmem, MCK__40_, MCK_IntRegs, MCK__43_, MCK__43_, MCK_ModRegs, MCK__41_ }, },
8733 { 0 /* */, Hexagon::V6_vL32b_tmp_pi, Convert__Reg1_0__Reg1_6__Tie1_0_0__s3_0Imm1_10, AMFBS_UseHVXV60, { MCK_HvxVR, MCK__DOT_, MCK_tmp, MCK__61_, MCK_vmem, MCK__40_, MCK_IntRegs, MCK__43_, MCK__43_, MCK__HASH_, MCK_s3_0Imm, MCK__41_ }, },
8885 { 0 /* */, Hexagon::V6_vL32b_nt_tmp_ai, Convert__Reg1_0__Reg1_6__s4_0Imm1_9, AMFBS_UseHVXV60, { MCK_HvxVR, MCK__DOT_, MCK_tmp, MCK__61_, MCK_vmem, MCK__40_, MCK_IntRegs, MCK__43_, MCK__HASH_, MCK_s4_0Imm, MCK__41_, MCK__COLON_, MCK_nt }, },
8886 { 0 /* */, Hexagon::V6_vL32b_nt_tmp_ppu, Convert__Reg1_0__Reg1_6__Tie1_0_0__Reg1_9, AMFBS_UseHVXV60, { MCK_HvxVR, MCK__DOT_, MCK_tmp, MCK__61_, MCK_vmem, MCK__40_, MCK_IntRegs, MCK__43_, MCK__43_, MCK_ModRegs, MCK__41_, MCK__COLON_, MCK_nt }, },
9038 { 0 /* */, Hexagon::V6_vL32b_nt_tmp_pi, Convert__Reg1_0__Reg1_6__Tie1_0_0__s3_0Imm1_10, AMFBS_UseHVXV60, { MCK_HvxVR, MCK__DOT_, MCK_tmp, MCK__61_, MCK_vmem, MCK__40_, MCK_IntRegs, MCK__43_, MCK__43_, MCK__HASH_, MCK_s3_0Imm, MCK__41_, MCK__COLON_, MCK_nt }, },
9472 { 158 /* if */, Hexagon::V6_vL32b_tmp_pred_ai, Convert__Reg1_4__Reg1_2__Reg1_10__imm_95_0, AMFBS_UseHVX, { MCK_if, MCK__40_, MCK_PredRegs, MCK__41_, MCK_HvxVR, MCK__DOT_, MCK_tmp, MCK__61_, MCK_vmem, MCK__40_, MCK_IntRegs, MCK__41_ }, },
9513 { 158 /* if */, Hexagon::V6_vL32b_npred_ai, Convert__Reg1_5__Reg1_3__Reg1_11__imm_95_0, AMFBS_UseHVX, { MCK_if, MCK__40_, MCK__EXCLAIM_, MCK_PredRegs, MCK__41_, MCK_HvxVR, MCK__DOT_, MCK_tmp, MCK__61_, MCK_vmem, MCK__40_, MCK_IntRegs, MCK__41_ }, },
9639 { 158 /* if */, Hexagon::V6_vL32b_nt_tmp_pred_ai, Convert__Reg1_4__Reg1_2__Reg1_10__imm_95_0, AMFBS_UseHVX, { MCK_if, MCK__40_, MCK_PredRegs, MCK__41_, MCK_HvxVR, MCK__DOT_, MCK_tmp, MCK__61_, MCK_vmem, MCK__40_, MCK_IntRegs, MCK__41_, MCK__COLON_, MCK_nt }, },
9669 { 158 /* if */, Hexagon::V6_vL32b_nt_npred_ai, Convert__Reg1_5__Reg1_3__Reg1_11__imm_95_0, AMFBS_UseHVX, { MCK_if, MCK__40_, MCK__EXCLAIM_, MCK_PredRegs, MCK__41_, MCK_HvxVR, MCK__DOT_, MCK_tmp, MCK__61_, MCK_vmem, MCK__40_, MCK_IntRegs, MCK__41_, MCK__COLON_, MCK_nt }, },
9690 { 158 /* if */, Hexagon::V6_vL32b_tmp_pred_ai, Convert__Reg1_4__Reg1_2__Reg1_10__s4_0Imm1_13, AMFBS_UseHVXV62, { MCK_if, MCK__40_, MCK_PredRegs, MCK__41_, MCK_HvxVR, MCK__DOT_, MCK_tmp, MCK__61_, MCK_vmem, MCK__40_, MCK_IntRegs, MCK__43_, MCK__HASH_, MCK_s4_0Imm, MCK__41_ }, },
9691 { 158 /* if */, Hexagon::V6_vL32b_tmp_pred_ppu, Convert__Reg1_4__Reg1_10__Reg1_2__Tie1_0_0__Reg1_13, AMFBS_UseHVXV62, { MCK_if, MCK__40_, MCK_PredRegs, MCK__41_, MCK_HvxVR, MCK__DOT_, MCK_tmp, MCK__61_, MCK_vmem, MCK__40_, MCK_IntRegs, MCK__43_, MCK__43_, MCK_ModRegs, MCK__41_ }, },
9722 { 158 /* if */, Hexagon::V6_vL32b_tmp_npred_ai, Convert__Reg1_5__Reg1_3__Reg1_11__s4_0Imm1_14, AMFBS_UseHVXV62, { MCK_if, MCK__40_, MCK__EXCLAIM_, MCK_PredRegs, MCK__41_, MCK_HvxVR, MCK__DOT_, MCK_tmp, MCK__61_, MCK_vmem, MCK__40_, MCK_IntRegs, MCK__43_, MCK__HASH_, MCK_s4_0Imm, MCK__41_ }, },
9723 { 158 /* if */, Hexagon::V6_vL32b_tmp_npred_ppu, Convert__Reg1_5__Reg1_11__Reg1_3__Tie1_0_0__Reg1_14, AMFBS_UseHVXV62, { MCK_if, MCK__40_, MCK__EXCLAIM_, MCK_PredRegs, MCK__41_, MCK_HvxVR, MCK__DOT_, MCK_tmp, MCK__61_, MCK_vmem, MCK__40_, MCK_IntRegs, MCK__43_, MCK__43_, MCK_ModRegs, MCK__41_ }, },
9774 { 158 /* if */, Hexagon::V6_vL32b_tmp_pred_pi, Convert__Reg1_4__Reg1_10__Reg1_2__Tie1_0_0__s3_0Imm1_14, AMFBS_UseHVXV62, { MCK_if, MCK__40_, MCK_PredRegs, MCK__41_, MCK_HvxVR, MCK__DOT_, MCK_tmp, MCK__61_, MCK_vmem, MCK__40_, MCK_IntRegs, MCK__43_, MCK__43_, MCK__HASH_, MCK_s3_0Imm, MCK__41_ }, },
9819 { 158 /* if */, Hexagon::V6_vL32b_tmp_npred_pi, Convert__Reg1_5__Reg1_11__Reg1_3__Tie1_0_0__s3_0Imm1_15, AMFBS_UseHVXV62, { MCK_if, MCK__40_, MCK__EXCLAIM_, MCK_PredRegs, MCK__41_, MCK_HvxVR, MCK__DOT_, MCK_tmp, MCK__61_, MCK_vmem, MCK__40_, MCK_IntRegs, MCK__43_, MCK__43_, MCK__HASH_, MCK_s3_0Imm, MCK__41_ }, },
9850 { 158 /* if */, Hexagon::V6_vL32b_nt_tmp_pred_ai, Convert__Reg1_4__Reg1_2__Reg1_10__s4_0Imm1_13, AMFBS_UseHVXV62, { MCK_if, MCK__40_, MCK_PredRegs, MCK__41_, MCK_HvxVR, MCK__DOT_, MCK_tmp, MCK__61_, MCK_vmem, MCK__40_, MCK_IntRegs, MCK__43_, MCK__HASH_, MCK_s4_0Imm, MCK__41_, MCK__COLON_, MCK_nt }, },
9851 { 158 /* if */, Hexagon::V6_vL32b_nt_tmp_pred_ppu, Convert__Reg1_4__Reg1_10__Reg1_2__Tie1_0_0__Reg1_13, AMFBS_UseHVXV62, { MCK_if, MCK__40_, MCK_PredRegs, MCK__41_, MCK_HvxVR, MCK__DOT_, MCK_tmp, MCK__61_, MCK_vmem, MCK__40_, MCK_IntRegs, MCK__43_, MCK__43_, MCK_ModRegs, MCK__41_, MCK__COLON_, MCK_nt }, },
9870 { 158 /* if */, Hexagon::V6_vL32b_nt_tmp_npred_ai, Convert__Reg1_5__Reg1_3__Reg1_11__s4_0Imm1_14, AMFBS_UseHVXV62, { MCK_if, MCK__40_, MCK__EXCLAIM_, MCK_PredRegs, MCK__41_, MCK_HvxVR, MCK__DOT_, MCK_tmp, MCK__61_, MCK_vmem, MCK__40_, MCK_IntRegs, MCK__43_, MCK__HASH_, MCK_s4_0Imm, MCK__41_, MCK__COLON_, MCK_nt }, },
9871 { 158 /* if */, Hexagon::V6_vL32b_nt_tmp_npred_ppu, Convert__Reg1_5__Reg1_11__Reg1_3__Tie1_0_0__Reg1_14, AMFBS_UseHVXV62, { MCK_if, MCK__40_, MCK__EXCLAIM_, MCK_PredRegs, MCK__41_, MCK_HvxVR, MCK__DOT_, MCK_tmp, MCK__61_, MCK_vmem, MCK__40_, MCK_IntRegs, MCK__43_, MCK__43_, MCK_ModRegs, MCK__41_, MCK__COLON_, MCK_nt }, },
9885 { 158 /* if */, Hexagon::V6_vL32b_nt_tmp_pred_pi, Convert__Reg1_4__Reg1_10__Reg1_2__Tie1_0_0__s3_0Imm1_14, AMFBS_UseHVXV62, { MCK_if, MCK__40_, MCK_PredRegs, MCK__41_, MCK_HvxVR, MCK__DOT_, MCK_tmp, MCK__61_, MCK_vmem, MCK__40_, MCK_IntRegs, MCK__43_, MCK__43_, MCK__HASH_, MCK_s3_0Imm, MCK__41_, MCK__COLON_, MCK_nt }, },
9906 { 158 /* if */, Hexagon::V6_vL32b_nt_tmp_npred_pi, Convert__Reg1_5__Reg1_11__Reg1_3__Tie1_0_0__s3_0Imm1_15, AMFBS_UseHVXV62, { MCK_if, MCK__40_, MCK__EXCLAIM_, MCK_PredRegs, MCK__41_, MCK_HvxVR, MCK__DOT_, MCK_tmp, MCK__61_, MCK_vmem, MCK__40_, MCK_IntRegs, MCK__43_, MCK__43_, MCK__HASH_, MCK_s3_0Imm, MCK__41_, MCK__COLON_, MCK_nt }, },