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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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References
gen/lib/Target/Hexagon/HexagonGenAsmMatcher.inc 6434 case MCK_s4_2Imm: {
7407 case MCK_s4_2Imm: return "MCK_s4_2Imm";
8511 { 0 /* */, Hexagon::L2_loadbsw4_pi, Convert__Reg1_0__Reg1_4__Tie1_0_0__s4_2Imm1_8, AMFBS_None, { MCK_DoubleRegs, MCK__61_, MCK_membh, MCK__40_, MCK_IntRegs, MCK__43_, MCK__43_, MCK__HASH_, MCK_s4_2Imm, MCK__41_ }, },
8514 { 0 /* */, Hexagon::L2_loadbzw4_pi, Convert__Reg1_0__Reg1_4__Tie1_0_0__s4_2Imm1_8, AMFBS_None, { MCK_DoubleRegs, MCK__61_, MCK_memubh, MCK__40_, MCK_IntRegs, MCK__43_, MCK__43_, MCK__HASH_, MCK_s4_2Imm, MCK__41_ }, },
8545 { 0 /* */, Hexagon::L2_loadri_pi, Convert__Reg1_0__Reg1_4__Tie1_0_0__s4_2Imm1_8, AMFBS_None, { MCK_IntRegs, MCK__61_, MCK_memw, MCK__40_, MCK_IntRegs, MCK__43_, MCK__43_, MCK__HASH_, MCK_s4_2Imm, MCK__41_ }, },
9061 { 0 /* */, Hexagon::L2_loadbsw4_pci, Convert__Reg1_0__Reg1_4__Tie1_0_0__s4_2Imm1_8__Reg1_12, AMFBS_None, { MCK_DoubleRegs, MCK__61_, MCK_membh, MCK__40_, MCK_IntRegs, MCK__43_, MCK__43_, MCK__HASH_, MCK_s4_2Imm, MCK__COLON_, MCK_circ, MCK__40_, MCK_ModRegs, MCK__41_, MCK__41_ }, },
9064 { 0 /* */, Hexagon::L2_loadbzw4_pci, Convert__Reg1_0__Reg1_4__Tie1_0_0__s4_2Imm1_8__Reg1_12, AMFBS_None, { MCK_DoubleRegs, MCK__61_, MCK_memubh, MCK__40_, MCK_IntRegs, MCK__43_, MCK__43_, MCK__HASH_, MCK_s4_2Imm, MCK__COLON_, MCK_circ, MCK__40_, MCK_ModRegs, MCK__41_, MCK__41_ }, },
9109 { 0 /* */, Hexagon::L2_loadri_pci, Convert__Reg1_0__Reg1_4__Tie1_0_0__s4_2Imm1_8__Reg1_12, AMFBS_None, { MCK_IntRegs, MCK__61_, MCK_memw, MCK__40_, MCK_IntRegs, MCK__43_, MCK__43_, MCK__HASH_, MCK_s4_2Imm, MCK__COLON_, MCK_circ, MCK__40_, MCK_ModRegs, MCK__41_, MCK__41_ }, },
9628 { 158 /* if */, Hexagon::S2_pstorerit_pi, Convert__Reg1_6__Reg1_2__Tie0_0_0__s4_2Imm1_10__Reg1_13, AMFBS_None, { MCK_if, MCK__40_, MCK_PredRegs, MCK__41_, MCK_memw, MCK__40_, MCK_IntRegs, MCK__43_, MCK__43_, MCK__HASH_, MCK_s4_2Imm, MCK__41_, MCK__61_, MCK_IntRegs }, },
9637 { 158 /* if */, Hexagon::L2_ploadrit_pi, Convert__Reg1_4__Reg1_8__Reg1_2__Tie1_0_0__s4_2Imm1_12, AMFBS_None, { MCK_if, MCK__40_, MCK_PredRegs, MCK__41_, MCK_IntRegs, MCK__61_, MCK_memw, MCK__40_, MCK_IntRegs, MCK__43_, MCK__43_, MCK__HASH_, MCK_s4_2Imm, MCK__41_ }, },
9659 { 158 /* if */, Hexagon::S2_pstorerif_pi, Convert__Reg1_7__Reg1_3__Tie0_0_0__s4_2Imm1_11__Reg1_14, AMFBS_None, { MCK_if, MCK__40_, MCK__EXCLAIM_, MCK_PredRegs, MCK__41_, MCK_memw, MCK__40_, MCK_IntRegs, MCK__43_, MCK__43_, MCK__HASH_, MCK_s4_2Imm, MCK__41_, MCK__61_, MCK_IntRegs }, },
9667 { 158 /* if */, Hexagon::L2_ploadrif_pi, Convert__Reg1_5__Reg1_9__Reg1_3__Tie1_0_0__s4_2Imm1_13, AMFBS_None, { MCK_if, MCK__40_, MCK__EXCLAIM_, MCK_PredRegs, MCK__41_, MCK_IntRegs, MCK__61_, MCK_memw, MCK__40_, MCK_IntRegs, MCK__43_, MCK__43_, MCK__HASH_, MCK_s4_2Imm, MCK__41_ }, },
9763 { 158 /* if */, Hexagon::S2_pstorerinewt_pi, Convert__Reg1_6__Reg1_2__Tie0_0_0__s4_2Imm1_10__Reg1_13, AMFBS_None, { MCK_if, MCK__40_, MCK_PredRegs, MCK__41_, MCK_memw, MCK__40_, MCK_IntRegs, MCK__43_, MCK__43_, MCK__HASH_, MCK_s4_2Imm, MCK__41_, MCK__61_, MCK_IntRegs, MCK__DOT_, MCK_new }, },
9782 { 158 /* if */, Hexagon::S2_pstoreritnew_pi, Convert__Reg1_8__Reg1_2__Tie0_0_0__s4_2Imm1_12__Reg1_15, AMFBS_None, { MCK_if, MCK__40_, MCK_PredRegs, MCK__DOT_, MCK_new, MCK__41_, MCK_memw, MCK__40_, MCK_IntRegs, MCK__43_, MCK__43_, MCK__HASH_, MCK_s4_2Imm, MCK__41_, MCK__61_, MCK_IntRegs }, },
9790 { 158 /* if */, Hexagon::L2_ploadritnew_pi, Convert__Reg1_6__Reg1_10__Reg1_2__Tie1_0_0__s4_2Imm1_14, AMFBS_None, { MCK_if, MCK__40_, MCK_PredRegs, MCK__DOT_, MCK_new, MCK__41_, MCK_IntRegs, MCK__61_, MCK_memw, MCK__40_, MCK_IntRegs, MCK__43_, MCK__43_, MCK__HASH_, MCK_s4_2Imm, MCK__41_ }, },
9808 { 158 /* if */, Hexagon::S2_pstorerinewf_pi, Convert__Reg1_7__Reg1_3__Tie0_0_0__s4_2Imm1_11__Reg1_14, AMFBS_None, { MCK_if, MCK__40_, MCK__EXCLAIM_, MCK_PredRegs, MCK__41_, MCK_memw, MCK__40_, MCK_IntRegs, MCK__43_, MCK__43_, MCK__HASH_, MCK_s4_2Imm, MCK__41_, MCK__61_, MCK_IntRegs, MCK__DOT_, MCK_new }, },
9827 { 158 /* if */, Hexagon::S2_pstorerifnew_pi, Convert__Reg1_9__Reg1_3__Tie0_0_0__s4_2Imm1_13__Reg1_16, AMFBS_None, { MCK_if, MCK__40_, MCK__EXCLAIM_, MCK_PredRegs, MCK__DOT_, MCK_new, MCK__41_, MCK_memw, MCK__40_, MCK_IntRegs, MCK__43_, MCK__43_, MCK__HASH_, MCK_s4_2Imm, MCK__41_, MCK__61_, MCK_IntRegs }, },
9835 { 158 /* if */, Hexagon::L2_ploadrifnew_pi, Convert__Reg1_7__Reg1_11__Reg1_3__Tie1_0_0__s4_2Imm1_15, AMFBS_None, { MCK_if, MCK__40_, MCK__EXCLAIM_, MCK_PredRegs, MCK__DOT_, MCK_new, MCK__41_, MCK_IntRegs, MCK__61_, MCK_memw, MCK__40_, MCK_IntRegs, MCK__43_, MCK__43_, MCK__HASH_, MCK_s4_2Imm, MCK__41_ }, },
9892 { 158 /* if */, Hexagon::S2_pstorerinewtnew_pi, Convert__Reg1_8__Reg1_2__Tie0_0_0__s4_2Imm1_12__Reg1_15, AMFBS_None, { MCK_if, MCK__40_, MCK_PredRegs, MCK__DOT_, MCK_new, MCK__41_, MCK_memw, MCK__40_, MCK_IntRegs, MCK__43_, MCK__43_, MCK__HASH_, MCK_s4_2Imm, MCK__41_, MCK__61_, MCK_IntRegs, MCK__DOT_, MCK_new }, },
9913 { 158 /* if */, Hexagon::S2_pstorerinewfnew_pi, Convert__Reg1_9__Reg1_3__Tie0_0_0__s4_2Imm1_13__Reg1_16, AMFBS_None, { MCK_if, MCK__40_, MCK__EXCLAIM_, MCK_PredRegs, MCK__DOT_, MCK_new, MCK__41_, MCK_memw, MCK__40_, MCK_IntRegs, MCK__43_, MCK__43_, MCK__HASH_, MCK_s4_2Imm, MCK__41_, MCK__61_, MCK_IntRegs, MCK__DOT_, MCK_new }, },
10075 { 239 /* memw */, Hexagon::S2_storeri_pi, Convert__Reg1_2__Tie0_0_0__s4_2Imm1_6__Reg1_9, AMFBS_None, { MCK_memw, MCK__40_, MCK_IntRegs, MCK__43_, MCK__43_, MCK__HASH_, MCK_s4_2Imm, MCK__41_, MCK__61_, MCK_IntRegs }, },
10083 { 239 /* memw */, Hexagon::S2_storerinew_pi, Convert__Reg1_2__Tie0_0_0__s4_2Imm1_6__Reg1_9, AMFBS_None, { MCK_memw, MCK__40_, MCK_IntRegs, MCK__43_, MCK__43_, MCK__HASH_, MCK_s4_2Imm, MCK__41_, MCK__61_, MCK_IntRegs, MCK__DOT_, MCK_new }, },
10091 { 239 /* memw */, Hexagon::S2_storeri_pci, Convert__Reg1_2__Tie0_0_0__s4_2Imm1_6__Reg1_10__Reg1_14, AMFBS_None, { MCK_memw, MCK__40_, MCK_IntRegs, MCK__43_, MCK__43_, MCK__HASH_, MCK_s4_2Imm, MCK__COLON_, MCK_circ, MCK__40_, MCK_ModRegs, MCK__41_, MCK__41_, MCK__61_, MCK_IntRegs }, },
10094 { 239 /* memw */, Hexagon::S2_storerinew_pci, Convert__Reg1_2__Tie0_0_0__s4_2Imm1_6__Reg1_10__Reg1_14, AMFBS_None, { MCK_memw, MCK__40_, MCK_IntRegs, MCK__43_, MCK__43_, MCK__HASH_, MCK_s4_2Imm, MCK__COLON_, MCK_circ, MCK__40_, MCK_ModRegs, MCK__41_, MCK__41_, MCK__61_, MCK_IntRegs, MCK__DOT_, MCK_new }, },