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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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References
gen/lib/Target/Hexagon/HexagonGenAsmMatcher.inc 6427 case MCK_s4_1Imm: {
7406 case MCK_s4_1Imm: return "MCK_s4_1Imm";
8513 { 0 /* */, Hexagon::L2_loadalignh_pi, Convert__Reg1_0__Reg1_4__Tie0_0_0__Tie1_0_0__s4_1Imm1_8, AMFBS_None, { MCK_DoubleRegs, MCK__61_, MCK_memh_95_fifo, MCK__40_, MCK_IntRegs, MCK__43_, MCK__43_, MCK__HASH_, MCK_s4_1Imm, MCK__41_ }, },
8540 { 0 /* */, Hexagon::L2_loadbsw2_pi, Convert__Reg1_0__Reg1_4__Tie1_0_0__s4_1Imm1_8, AMFBS_None, { MCK_IntRegs, MCK__61_, MCK_membh, MCK__40_, MCK_IntRegs, MCK__43_, MCK__43_, MCK__HASH_, MCK_s4_1Imm, MCK__41_ }, },
8541 { 0 /* */, Hexagon::L2_loadrh_pi, Convert__Reg1_0__Reg1_4__Tie1_0_0__s4_1Imm1_8, AMFBS_None, { MCK_IntRegs, MCK__61_, MCK_memh, MCK__40_, MCK_IntRegs, MCK__43_, MCK__43_, MCK__HASH_, MCK_s4_1Imm, MCK__41_ }, },
8543 { 0 /* */, Hexagon::L2_loadbzw2_pi, Convert__Reg1_0__Reg1_4__Tie1_0_0__s4_1Imm1_8, AMFBS_None, { MCK_IntRegs, MCK__61_, MCK_memubh, MCK__40_, MCK_IntRegs, MCK__43_, MCK__43_, MCK__HASH_, MCK_s4_1Imm, MCK__41_ }, },
8544 { 0 /* */, Hexagon::L2_loadruh_pi, Convert__Reg1_0__Reg1_4__Tie1_0_0__s4_1Imm1_8, AMFBS_None, { MCK_IntRegs, MCK__61_, MCK_memuh, MCK__40_, MCK_IntRegs, MCK__43_, MCK__43_, MCK__HASH_, MCK_s4_1Imm, MCK__41_ }, },
9063 { 0 /* */, Hexagon::L2_loadalignh_pci, Convert__Reg1_0__Reg1_4__Tie0_0_0__Tie1_0_0__s4_1Imm1_8__Reg1_12, AMFBS_None, { MCK_DoubleRegs, MCK__61_, MCK_memh_95_fifo, MCK__40_, MCK_IntRegs, MCK__43_, MCK__43_, MCK__HASH_, MCK_s4_1Imm, MCK__COLON_, MCK_circ, MCK__40_, MCK_ModRegs, MCK__41_, MCK__41_ }, },
9104 { 0 /* */, Hexagon::L2_loadbsw2_pci, Convert__Reg1_0__Reg1_4__Tie1_0_0__s4_1Imm1_8__Reg1_12, AMFBS_None, { MCK_IntRegs, MCK__61_, MCK_membh, MCK__40_, MCK_IntRegs, MCK__43_, MCK__43_, MCK__HASH_, MCK_s4_1Imm, MCK__COLON_, MCK_circ, MCK__40_, MCK_ModRegs, MCK__41_, MCK__41_ }, },
9105 { 0 /* */, Hexagon::L2_loadrh_pci, Convert__Reg1_0__Reg1_4__Tie1_0_0__s4_1Imm1_8__Reg1_12, AMFBS_None, { MCK_IntRegs, MCK__61_, MCK_memh, MCK__40_, MCK_IntRegs, MCK__43_, MCK__43_, MCK__HASH_, MCK_s4_1Imm, MCK__COLON_, MCK_circ, MCK__40_, MCK_ModRegs, MCK__41_, MCK__41_ }, },
9107 { 0 /* */, Hexagon::L2_loadbzw2_pci, Convert__Reg1_0__Reg1_4__Tie1_0_0__s4_1Imm1_8__Reg1_12, AMFBS_None, { MCK_IntRegs, MCK__61_, MCK_memubh, MCK__40_, MCK_IntRegs, MCK__43_, MCK__43_, MCK__HASH_, MCK_s4_1Imm, MCK__COLON_, MCK_circ, MCK__40_, MCK_ModRegs, MCK__41_, MCK__41_ }, },
9108 { 0 /* */, Hexagon::L2_loadruh_pci, Convert__Reg1_0__Reg1_4__Tie1_0_0__s4_1Imm1_8__Reg1_12, AMFBS_None, { MCK_IntRegs, MCK__61_, MCK_memuh, MCK__40_, MCK_IntRegs, MCK__43_, MCK__43_, MCK__HASH_, MCK_s4_1Imm, MCK__COLON_, MCK_circ, MCK__40_, MCK_ModRegs, MCK__41_, MCK__41_ }, },
9626 { 158 /* if */, Hexagon::S2_pstorerht_pi, Convert__Reg1_6__Reg1_2__Tie0_0_0__s4_1Imm1_10__Reg1_13, AMFBS_None, { MCK_if, MCK__40_, MCK_PredRegs, MCK__41_, MCK_memh, MCK__40_, MCK_IntRegs, MCK__43_, MCK__43_, MCK__HASH_, MCK_s4_1Imm, MCK__41_, MCK__61_, MCK_IntRegs }, },
9634 { 158 /* if */, Hexagon::L2_ploadrht_pi, Convert__Reg1_4__Reg1_8__Reg1_2__Tie1_0_0__s4_1Imm1_12, AMFBS_None, { MCK_if, MCK__40_, MCK_PredRegs, MCK__41_, MCK_IntRegs, MCK__61_, MCK_memh, MCK__40_, MCK_IntRegs, MCK__43_, MCK__43_, MCK__HASH_, MCK_s4_1Imm, MCK__41_ }, },
9636 { 158 /* if */, Hexagon::L2_ploadruht_pi, Convert__Reg1_4__Reg1_8__Reg1_2__Tie1_0_0__s4_1Imm1_12, AMFBS_None, { MCK_if, MCK__40_, MCK_PredRegs, MCK__41_, MCK_IntRegs, MCK__61_, MCK_memuh, MCK__40_, MCK_IntRegs, MCK__43_, MCK__43_, MCK__HASH_, MCK_s4_1Imm, MCK__41_ }, },
9657 { 158 /* if */, Hexagon::S2_pstorerhf_pi, Convert__Reg1_7__Reg1_3__Tie0_0_0__s4_1Imm1_11__Reg1_14, AMFBS_None, { MCK_if, MCK__40_, MCK__EXCLAIM_, MCK_PredRegs, MCK__41_, MCK_memh, MCK__40_, MCK_IntRegs, MCK__43_, MCK__43_, MCK__HASH_, MCK_s4_1Imm, MCK__41_, MCK__61_, MCK_IntRegs }, },
9664 { 158 /* if */, Hexagon::L2_ploadrhf_pi, Convert__Reg1_5__Reg1_9__Reg1_3__Tie1_0_0__s4_1Imm1_13, AMFBS_None, { MCK_if, MCK__40_, MCK__EXCLAIM_, MCK_PredRegs, MCK__41_, MCK_IntRegs, MCK__61_, MCK_memh, MCK__40_, MCK_IntRegs, MCK__43_, MCK__43_, MCK__HASH_, MCK_s4_1Imm, MCK__41_ }, },
9666 { 158 /* if */, Hexagon::L2_ploadruhf_pi, Convert__Reg1_5__Reg1_9__Reg1_3__Tie1_0_0__s4_1Imm1_13, AMFBS_None, { MCK_if, MCK__40_, MCK__EXCLAIM_, MCK_PredRegs, MCK__41_, MCK_IntRegs, MCK__61_, MCK_memuh, MCK__40_, MCK_IntRegs, MCK__43_, MCK__43_, MCK__HASH_, MCK_s4_1Imm, MCK__41_ }, },
9760 { 158 /* if */, Hexagon::S2_pstorerft_pi, Convert__Reg1_6__Reg1_2__Tie0_0_0__s4_1Imm1_10__Reg1_13, AMFBS_None, { MCK_if, MCK__40_, MCK_PredRegs, MCK__41_, MCK_memh, MCK__40_, MCK_IntRegs, MCK__43_, MCK__43_, MCK__HASH_, MCK_s4_1Imm, MCK__41_, MCK__61_, MCK_IntRegs, MCK__DOT_, MCK_h }, },
9761 { 158 /* if */, Hexagon::S2_pstorerhnewt_pi, Convert__Reg1_6__Reg1_2__Tie0_0_0__s4_1Imm1_10__Reg1_13, AMFBS_None, { MCK_if, MCK__40_, MCK_PredRegs, MCK__41_, MCK_memh, MCK__40_, MCK_IntRegs, MCK__43_, MCK__43_, MCK__HASH_, MCK_s4_1Imm, MCK__41_, MCK__61_, MCK_IntRegs, MCK__DOT_, MCK_new }, },
9780 { 158 /* if */, Hexagon::S2_pstorerhtnew_pi, Convert__Reg1_8__Reg1_2__Tie0_0_0__s4_1Imm1_12__Reg1_15, AMFBS_None, { MCK_if, MCK__40_, MCK_PredRegs, MCK__DOT_, MCK_new, MCK__41_, MCK_memh, MCK__40_, MCK_IntRegs, MCK__43_, MCK__43_, MCK__HASH_, MCK_s4_1Imm, MCK__41_, MCK__61_, MCK_IntRegs }, },
9787 { 158 /* if */, Hexagon::L2_ploadrhtnew_pi, Convert__Reg1_6__Reg1_10__Reg1_2__Tie1_0_0__s4_1Imm1_14, AMFBS_None, { MCK_if, MCK__40_, MCK_PredRegs, MCK__DOT_, MCK_new, MCK__41_, MCK_IntRegs, MCK__61_, MCK_memh, MCK__40_, MCK_IntRegs, MCK__43_, MCK__43_, MCK__HASH_, MCK_s4_1Imm, MCK__41_ }, },
9789 { 158 /* if */, Hexagon::L2_ploadruhtnew_pi, Convert__Reg1_6__Reg1_10__Reg1_2__Tie1_0_0__s4_1Imm1_14, AMFBS_None, { MCK_if, MCK__40_, MCK_PredRegs, MCK__DOT_, MCK_new, MCK__41_, MCK_IntRegs, MCK__61_, MCK_memuh, MCK__40_, MCK_IntRegs, MCK__43_, MCK__43_, MCK__HASH_, MCK_s4_1Imm, MCK__41_ }, },
9805 { 158 /* if */, Hexagon::S2_pstorerff_pi, Convert__Reg1_7__Reg1_3__Tie0_0_0__s4_1Imm1_11__Reg1_14, AMFBS_None, { MCK_if, MCK__40_, MCK__EXCLAIM_, MCK_PredRegs, MCK__41_, MCK_memh, MCK__40_, MCK_IntRegs, MCK__43_, MCK__43_, MCK__HASH_, MCK_s4_1Imm, MCK__41_, MCK__61_, MCK_IntRegs, MCK__DOT_, MCK_h }, },
9806 { 158 /* if */, Hexagon::S2_pstorerhnewf_pi, Convert__Reg1_7__Reg1_3__Tie0_0_0__s4_1Imm1_11__Reg1_14, AMFBS_None, { MCK_if, MCK__40_, MCK__EXCLAIM_, MCK_PredRegs, MCK__41_, MCK_memh, MCK__40_, MCK_IntRegs, MCK__43_, MCK__43_, MCK__HASH_, MCK_s4_1Imm, MCK__41_, MCK__61_, MCK_IntRegs, MCK__DOT_, MCK_new }, },
9825 { 158 /* if */, Hexagon::S2_pstorerhfnew_pi, Convert__Reg1_9__Reg1_3__Tie0_0_0__s4_1Imm1_13__Reg1_16, AMFBS_None, { MCK_if, MCK__40_, MCK__EXCLAIM_, MCK_PredRegs, MCK__DOT_, MCK_new, MCK__41_, MCK_memh, MCK__40_, MCK_IntRegs, MCK__43_, MCK__43_, MCK__HASH_, MCK_s4_1Imm, MCK__41_, MCK__61_, MCK_IntRegs }, },
9832 { 158 /* if */, Hexagon::L2_ploadrhfnew_pi, Convert__Reg1_7__Reg1_11__Reg1_3__Tie1_0_0__s4_1Imm1_15, AMFBS_None, { MCK_if, MCK__40_, MCK__EXCLAIM_, MCK_PredRegs, MCK__DOT_, MCK_new, MCK__41_, MCK_IntRegs, MCK__61_, MCK_memh, MCK__40_, MCK_IntRegs, MCK__43_, MCK__43_, MCK__HASH_, MCK_s4_1Imm, MCK__41_ }, },
9834 { 158 /* if */, Hexagon::L2_ploadruhfnew_pi, Convert__Reg1_7__Reg1_11__Reg1_3__Tie1_0_0__s4_1Imm1_15, AMFBS_None, { MCK_if, MCK__40_, MCK__EXCLAIM_, MCK_PredRegs, MCK__DOT_, MCK_new, MCK__41_, MCK_IntRegs, MCK__61_, MCK_memuh, MCK__40_, MCK_IntRegs, MCK__43_, MCK__43_, MCK__HASH_, MCK_s4_1Imm, MCK__41_ }, },
9889 { 158 /* if */, Hexagon::S2_pstorerftnew_pi, Convert__Reg1_8__Reg1_2__Tie0_0_0__s4_1Imm1_12__Reg1_15, AMFBS_None, { MCK_if, MCK__40_, MCK_PredRegs, MCK__DOT_, MCK_new, MCK__41_, MCK_memh, MCK__40_, MCK_IntRegs, MCK__43_, MCK__43_, MCK__HASH_, MCK_s4_1Imm, MCK__41_, MCK__61_, MCK_IntRegs, MCK__DOT_, MCK_h }, },
9890 { 158 /* if */, Hexagon::S2_pstorerhnewtnew_pi, Convert__Reg1_8__Reg1_2__Tie0_0_0__s4_1Imm1_12__Reg1_15, AMFBS_None, { MCK_if, MCK__40_, MCK_PredRegs, MCK__DOT_, MCK_new, MCK__41_, MCK_memh, MCK__40_, MCK_IntRegs, MCK__43_, MCK__43_, MCK__HASH_, MCK_s4_1Imm, MCK__41_, MCK__61_, MCK_IntRegs, MCK__DOT_, MCK_new }, },
9910 { 158 /* if */, Hexagon::S2_pstorerffnew_pi, Convert__Reg1_9__Reg1_3__Tie0_0_0__s4_1Imm1_13__Reg1_16, AMFBS_None, { MCK_if, MCK__40_, MCK__EXCLAIM_, MCK_PredRegs, MCK__DOT_, MCK_new, MCK__41_, MCK_memh, MCK__40_, MCK_IntRegs, MCK__43_, MCK__43_, MCK__HASH_, MCK_s4_1Imm, MCK__41_, MCK__61_, MCK_IntRegs, MCK__DOT_, MCK_h }, },
9911 { 158 /* if */, Hexagon::S2_pstorerhnewfnew_pi, Convert__Reg1_9__Reg1_3__Tie0_0_0__s4_1Imm1_13__Reg1_16, AMFBS_None, { MCK_if, MCK__40_, MCK__EXCLAIM_, MCK_PredRegs, MCK__DOT_, MCK_new, MCK__41_, MCK_memh, MCK__40_, MCK_IntRegs, MCK__43_, MCK__43_, MCK__HASH_, MCK_s4_1Imm, MCK__41_, MCK__61_, MCK_IntRegs, MCK__DOT_, MCK_new }, },
10023 { 234 /* memh */, Hexagon::S2_storerh_pi, Convert__Reg1_2__Tie0_0_0__s4_1Imm1_6__Reg1_9, AMFBS_None, { MCK_memh, MCK__40_, MCK_IntRegs, MCK__43_, MCK__43_, MCK__HASH_, MCK_s4_1Imm, MCK__41_, MCK__61_, MCK_IntRegs }, },
10035 { 234 /* memh */, Hexagon::S2_storerf_pi, Convert__Reg1_2__Tie0_0_0__s4_1Imm1_6__Reg1_9, AMFBS_None, { MCK_memh, MCK__40_, MCK_IntRegs, MCK__43_, MCK__43_, MCK__HASH_, MCK_s4_1Imm, MCK__41_, MCK__61_, MCK_IntRegs, MCK__DOT_, MCK_h }, },
10036 { 234 /* memh */, Hexagon::S2_storerhnew_pi, Convert__Reg1_2__Tie0_0_0__s4_1Imm1_6__Reg1_9, AMFBS_None, { MCK_memh, MCK__40_, MCK_IntRegs, MCK__43_, MCK__43_, MCK__HASH_, MCK_s4_1Imm, MCK__41_, MCK__61_, MCK_IntRegs, MCK__DOT_, MCK_new }, },
10046 { 234 /* memh */, Hexagon::S2_storerh_pci, Convert__Reg1_2__Tie0_0_0__s4_1Imm1_6__Reg1_10__Reg1_14, AMFBS_None, { MCK_memh, MCK__40_, MCK_IntRegs, MCK__43_, MCK__43_, MCK__HASH_, MCK_s4_1Imm, MCK__COLON_, MCK_circ, MCK__40_, MCK_ModRegs, MCK__41_, MCK__41_, MCK__61_, MCK_IntRegs }, },
10051 { 234 /* memh */, Hexagon::S2_storerf_pci, Convert__Reg1_2__Tie0_0_0__s4_1Imm1_6__Reg1_10__Reg1_14, AMFBS_None, { MCK_memh, MCK__40_, MCK_IntRegs, MCK__43_, MCK__43_, MCK__HASH_, MCK_s4_1Imm, MCK__COLON_, MCK_circ, MCK__40_, MCK_ModRegs, MCK__41_, MCK__41_, MCK__61_, MCK_IntRegs, MCK__DOT_, MCK_h }, },
10052 { 234 /* memh */, Hexagon::S2_storerhnew_pci, Convert__Reg1_2__Tie0_0_0__s4_1Imm1_6__Reg1_10__Reg1_14, AMFBS_None, { MCK_memh, MCK__40_, MCK_IntRegs, MCK__43_, MCK__43_, MCK__HASH_, MCK_s4_1Imm, MCK__COLON_, MCK_circ, MCK__40_, MCK_ModRegs, MCK__41_, MCK__41_, MCK__61_, MCK_IntRegs, MCK__DOT_, MCK_new }, },