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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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References
gen/lib/Target/Hexagon/HexagonGenAsmMatcher.inc 3715 return MCK_mpyi; // "mpyi"
7007 case MCK_mpyi: return "MCK_mpyi";
7907 { 0 /* */, Hexagon::M2_mpyi, Convert__Reg1_0__Reg1_4__Reg1_5, AMFBS_None, { MCK_IntRegs, MCK__61_, MCK_mpyi, MCK__40_, MCK_IntRegs, MCK_IntRegs, MCK__41_ }, },
8140 { 0 /* */, Hexagon::M2_maci, Convert__Reg1_0__Tie0_0_0__Reg1_5__Reg1_6, AMFBS_None, { MCK_IntRegs, MCK__43_, MCK__61_, MCK_mpyi, MCK__40_, MCK_IntRegs, MCK_IntRegs, MCK__41_ }, },
8148 { 0 /* */, Hexagon::M2_mnaci, Convert__Reg1_0__Tie0_0_0__Reg1_5__Reg1_6, AMFBS_HasV66, { MCK_IntRegs, MCK__MINUS_, MCK__61_, MCK_mpyi, MCK__40_, MCK_IntRegs, MCK_IntRegs, MCK__41_ }, },
8166 { 0 /* */, Hexagon::M2_mpysmi, Convert__Reg1_0__Reg1_4__m32_0Imm1_6, AMFBS_None, { MCK_IntRegs, MCK__61_, MCK_mpyi, MCK__40_, MCK_IntRegs, MCK__HASH_, MCK_m32_0Imm, MCK__41_ }, },
8361 { 0 /* */, Hexagon::M2_macsip, Convert__Reg1_0__Tie0_0_0__Reg1_5__u32_0Imm1_7, AMFBS_None, { MCK_IntRegs, MCK__43_, MCK__61_, MCK_mpyi, MCK__40_, MCK_IntRegs, MCK__HASH_, MCK_u32_0Imm, MCK__41_ }, },
8367 { 0 /* */, Hexagon::M2_macsin, Convert__Reg1_0__Tie0_0_0__Reg1_5__u32_0Imm1_7, AMFBS_None, { MCK_IntRegs, MCK__MINUS_, MCK__61_, MCK_mpyi, MCK__40_, MCK_IntRegs, MCK__HASH_, MCK_u32_0Imm, MCK__41_ }, },
8370 { 0 /* */, Hexagon::M2_mpysip, Convert__Reg1_0__Reg1_5__u32_0Imm1_7, AMFBS_None, { MCK_IntRegs, MCK__61_, MCK__43_, MCK_mpyi, MCK__40_, MCK_IntRegs, MCK__HASH_, MCK_u32_0Imm, MCK__41_ }, },
8371 { 0 /* */, Hexagon::M2_mpysin, Convert__Reg1_0__Reg1_5__u8_0Imm1_7, AMFBS_None, { MCK_IntRegs, MCK__61_, MCK__MINUS_, MCK_mpyi, MCK__40_, MCK_IntRegs, MCK__HASH_, MCK_u8_0Imm, MCK__41_ }, },
8623 { 0 /* */, Hexagon::M4_mpyrr_addr, Convert__Reg1_0__Reg1_4__Tie0_0_7__Reg1_8, AMFBS_None, { MCK_IntRegs, MCK__61_, MCK_add, MCK__40_, MCK_IntRegs, MCK_mpyi, MCK__40_, MCK_IntRegs, MCK_IntRegs, MCK__41_, MCK__41_ }, },
8710 { 0 /* */, Hexagon::M4_mpyrr_addi, Convert__Reg1_0__u32_0Imm1_5__Reg1_8__Reg1_9, AMFBS_None, { MCK_IntRegs, MCK__61_, MCK_add, MCK__40_, MCK__HASH_, MCK_u32_0Imm, MCK_mpyi, MCK__40_, MCK_IntRegs, MCK_IntRegs, MCK__41_, MCK__41_ }, },
8712 { 0 /* */, Hexagon::M4_mpyri_addr_u2, Convert__Reg1_0__Reg1_4__u6_2Imm1_8__Reg1_9, AMFBS_None, { MCK_IntRegs, MCK__61_, MCK_add, MCK__40_, MCK_IntRegs, MCK_mpyi, MCK__40_, MCK__HASH_, MCK_u6_2Imm, MCK_IntRegs, MCK__41_, MCK__41_ }, },
8713 { 0 /* */, Hexagon::M4_mpyri_addr, Convert__Reg1_0__Reg1_4__Reg1_7__u32_0Imm1_9, AMFBS_None, { MCK_IntRegs, MCK__61_, MCK_add, MCK__40_, MCK_IntRegs, MCK_mpyi, MCK__40_, MCK_IntRegs, MCK__HASH_, MCK_u32_0Imm, MCK__41_, MCK__41_ }, },
8826 { 0 /* */, Hexagon::M4_mpyri_addi, Convert__Reg1_0__u32_0Imm1_5__Reg1_8__u6_0Imm1_10, AMFBS_None, { MCK_IntRegs, MCK__61_, MCK_add, MCK__40_, MCK__HASH_, MCK_u32_0Imm, MCK_mpyi, MCK__40_, MCK_IntRegs, MCK__HASH_, MCK_u6_0Imm, MCK__41_, MCK__41_ }, },