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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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References
gen/lib/Target/Hexagon/HexagonGenAsmMatcher.inc 3986 return MCK_memuh; // "memuh"
7000 case MCK_memuh: return "MCK_memuh";
7681 { 0 /* */, Hexagon::L2_loadruh_io, Convert__Reg1_0__Reg1_4__imm_95_0, AMFBS_None, { MCK_IntRegs, MCK__61_, MCK_memuh, MCK__40_, MCK_IntRegs, MCK__41_ }, },
7901 { 0 /* */, Hexagon::PS_loadruhabs, Convert__Reg1_0__u31_1Imm1_5, AMFBS_None, { MCK_IntRegs, MCK__61_, MCK_memuh, MCK__40_, MCK__HASH_, MCK_u31_1Imm, MCK__41_ }, },
8396 { 0 /* */, Hexagon::L2_loadruhgp, Convert__Reg1_0__u31_1Imm1_7, AMFBS_None, { MCK_IntRegs, MCK__61_, MCK_memuh, MCK__40_, MCK_GP, MCK__43_, MCK__HASH_, MCK_u31_1Imm, MCK__41_ }, },
8397 { 0 /* */, Hexagon::L2_loadruh_io, Convert__Reg1_0__Reg1_4__s31_1Imm1_7, AMFBS_None, { MCK_IntRegs, MCK__61_, MCK_memuh, MCK__40_, MCK_IntRegs, MCK__43_, MCK__HASH_, MCK_s31_1Imm, MCK__41_ }, },
8398 { 0 /* */, Hexagon::L2_loadruh_pr, Convert__Reg1_0__Reg1_4__Tie1_0_0__Reg1_7, AMFBS_None, { MCK_IntRegs, MCK__61_, MCK_memuh, MCK__40_, MCK_IntRegs, MCK__43_, MCK__43_, MCK_ModRegs, MCK__41_ }, },
8399 { 0 /* */, Hexagon::L4_loadruh_ap, Convert__Reg1_0__Reg1_4__u32_0Imm1_7, AMFBS_None, { MCK_IntRegs, MCK__61_, MCK_memuh, MCK__40_, MCK_IntRegs, MCK__61_, MCK__HASH_, MCK_u32_0Imm, MCK__41_ }, },
8544 { 0 /* */, Hexagon::L2_loadruh_pi, Convert__Reg1_0__Reg1_4__Tie1_0_0__s4_1Imm1_8, AMFBS_None, { MCK_IntRegs, MCK__61_, MCK_memuh, MCK__40_, MCK_IntRegs, MCK__43_, MCK__43_, MCK__HASH_, MCK_s4_1Imm, MCK__41_ }, },
8635 { 0 /* */, Hexagon::L2_loadruh_pbr, Convert__Reg1_0__Reg1_4__Tie1_0_0__Reg1_7, AMFBS_None, { MCK_IntRegs, MCK__61_, MCK_memuh, MCK__40_, MCK_IntRegs, MCK__43_, MCK__43_, MCK_ModRegs, MCK__COLON_, MCK_brev, MCK__41_ }, },
8719 { 0 /* */, Hexagon::L4_loadruh_rr, Convert__Reg1_0__Reg1_4__Reg1_6__u2_0Imm1_10, AMFBS_None, { MCK_IntRegs, MCK__61_, MCK_memuh, MCK__40_, MCK_IntRegs, MCK__43_, MCK_IntRegs, MCK__LT_, MCK__LT_, MCK__HASH_, MCK_u2_0Imm, MCK__41_ }, },
8836 { 0 /* */, Hexagon::L4_loadruh_ur, Convert__Reg1_0__Reg1_4__u2_0Imm1_8__u32_0Imm1_11, AMFBS_None, { MCK_IntRegs, MCK__61_, MCK_memuh, MCK__40_, MCK_IntRegs, MCK__LT_, MCK__LT_, MCK__HASH_, MCK_u2_0Imm, MCK__43_, MCK__HASH_, MCK_u32_0Imm, MCK__41_ }, },
9030 { 0 /* */, Hexagon::L2_loadruh_pcr, Convert__Reg1_0__Reg1_4__Tie1_0_0__Reg1_11, AMFBS_None, { MCK_IntRegs, MCK__61_, MCK_memuh, MCK__40_, MCK_IntRegs, MCK__43_, MCK__43_, MCK_I, MCK__COLON_, MCK_circ, MCK__40_, MCK_ModRegs, MCK__41_, MCK__41_ }, },
9108 { 0 /* */, Hexagon::L2_loadruh_pci, Convert__Reg1_0__Reg1_4__Tie1_0_0__s4_1Imm1_8__Reg1_12, AMFBS_None, { MCK_IntRegs, MCK__61_, MCK_memuh, MCK__40_, MCK_IntRegs, MCK__43_, MCK__43_, MCK__HASH_, MCK_s4_1Imm, MCK__COLON_, MCK_circ, MCK__40_, MCK_ModRegs, MCK__41_, MCK__41_ }, },
9380 { 158 /* if */, Hexagon::L2_ploadruht_io, Convert__Reg1_4__Reg1_2__Reg1_8__imm_95_0, AMFBS_None, { MCK_if, MCK__40_, MCK_PredRegs, MCK__41_, MCK_IntRegs, MCK__61_, MCK_memuh, MCK__40_, MCK_IntRegs, MCK__41_ }, },
9405 { 158 /* if */, Hexagon::L2_ploadruhf_io, Convert__Reg1_5__Reg1_3__Reg1_9__imm_95_0, AMFBS_None, { MCK_if, MCK__40_, MCK__EXCLAIM_, MCK_PredRegs, MCK__41_, MCK_IntRegs, MCK__61_, MCK_memuh, MCK__40_, MCK_IntRegs, MCK__41_ }, },
9432 { 158 /* if */, Hexagon::L4_ploadruht_abs, Convert__Reg1_4__Reg1_2__u32_0Imm1_9, AMFBS_None, { MCK_if, MCK__40_, MCK_PredRegs, MCK__41_, MCK_IntRegs, MCK__61_, MCK_memuh, MCK__40_, MCK__HASH_, MCK_u32_0Imm, MCK__41_ }, },
9452 { 158 /* if */, Hexagon::L4_ploadruhf_abs, Convert__Reg1_5__Reg1_3__u32_0Imm1_10, AMFBS_None, { MCK_if, MCK__40_, MCK__EXCLAIM_, MCK_PredRegs, MCK__41_, MCK_IntRegs, MCK__61_, MCK_memuh, MCK__40_, MCK__HASH_, MCK_u32_0Imm, MCK__41_ }, },
9484 { 158 /* if */, Hexagon::L2_ploadruhtnew_io, Convert__Reg1_6__Reg1_2__Reg1_10__imm_95_0, AMFBS_None, { MCK_if, MCK__40_, MCK_PredRegs, MCK__DOT_, MCK_new, MCK__41_, MCK_IntRegs, MCK__61_, MCK_memuh, MCK__40_, MCK_IntRegs, MCK__41_ }, },
9525 { 158 /* if */, Hexagon::L2_ploadruhfnew_io, Convert__Reg1_7__Reg1_3__Reg1_11__imm_95_0, AMFBS_None, { MCK_if, MCK__40_, MCK__EXCLAIM_, MCK_PredRegs, MCK__DOT_, MCK_new, MCK__41_, MCK_IntRegs, MCK__61_, MCK_memuh, MCK__40_, MCK_IntRegs, MCK__41_ }, },
9551 { 158 /* if */, Hexagon::L2_ploadruht_io, Convert__Reg1_4__Reg1_2__Reg1_8__u31_1Imm1_11, AMFBS_None, { MCK_if, MCK__40_, MCK_PredRegs, MCK__41_, MCK_IntRegs, MCK__61_, MCK_memuh, MCK__40_, MCK_IntRegs, MCK__43_, MCK__HASH_, MCK_u31_1Imm, MCK__41_ }, },
9569 { 158 /* if */, Hexagon::L4_ploadruhtnew_abs, Convert__Reg1_6__Reg1_2__u32_0Imm1_11, AMFBS_None, { MCK_if, MCK__40_, MCK_PredRegs, MCK__DOT_, MCK_new, MCK__41_, MCK_IntRegs, MCK__61_, MCK_memuh, MCK__40_, MCK__HASH_, MCK_u32_0Imm, MCK__41_ }, },
9592 { 158 /* if */, Hexagon::L2_ploadruhf_io, Convert__Reg1_5__Reg1_3__Reg1_9__u31_1Imm1_12, AMFBS_None, { MCK_if, MCK__40_, MCK__EXCLAIM_, MCK_PredRegs, MCK__41_, MCK_IntRegs, MCK__61_, MCK_memuh, MCK__40_, MCK_IntRegs, MCK__43_, MCK__HASH_, MCK_u31_1Imm, MCK__41_ }, },
9610 { 158 /* if */, Hexagon::L4_ploadruhfnew_abs, Convert__Reg1_7__Reg1_3__u32_0Imm1_12, AMFBS_None, { MCK_if, MCK__40_, MCK__EXCLAIM_, MCK_PredRegs, MCK__DOT_, MCK_new, MCK__41_, MCK_IntRegs, MCK__61_, MCK_memuh, MCK__40_, MCK__HASH_, MCK_u32_0Imm, MCK__41_ }, },
9636 { 158 /* if */, Hexagon::L2_ploadruht_pi, Convert__Reg1_4__Reg1_8__Reg1_2__Tie1_0_0__s4_1Imm1_12, AMFBS_None, { MCK_if, MCK__40_, MCK_PredRegs, MCK__41_, MCK_IntRegs, MCK__61_, MCK_memuh, MCK__40_, MCK_IntRegs, MCK__43_, MCK__43_, MCK__HASH_, MCK_s4_1Imm, MCK__41_ }, },
9666 { 158 /* if */, Hexagon::L2_ploadruhf_pi, Convert__Reg1_5__Reg1_9__Reg1_3__Tie1_0_0__s4_1Imm1_13, AMFBS_None, { MCK_if, MCK__40_, MCK__EXCLAIM_, MCK_PredRegs, MCK__41_, MCK_IntRegs, MCK__61_, MCK_memuh, MCK__40_, MCK_IntRegs, MCK__43_, MCK__43_, MCK__HASH_, MCK_s4_1Imm, MCK__41_ }, },
9706 { 158 /* if */, Hexagon::L2_ploadruhtnew_io, Convert__Reg1_6__Reg1_2__Reg1_10__u31_1Imm1_13, AMFBS_None, { MCK_if, MCK__40_, MCK_PredRegs, MCK__DOT_, MCK_new, MCK__41_, MCK_IntRegs, MCK__61_, MCK_memuh, MCK__40_, MCK_IntRegs, MCK__43_, MCK__HASH_, MCK_u31_1Imm, MCK__41_ }, },
9738 { 158 /* if */, Hexagon::L2_ploadruhfnew_io, Convert__Reg1_7__Reg1_3__Reg1_11__u31_1Imm1_14, AMFBS_None, { MCK_if, MCK__40_, MCK__EXCLAIM_, MCK_PredRegs, MCK__DOT_, MCK_new, MCK__41_, MCK_IntRegs, MCK__61_, MCK_memuh, MCK__40_, MCK_IntRegs, MCK__43_, MCK__HASH_, MCK_u31_1Imm, MCK__41_ }, },
9771 { 158 /* if */, Hexagon::L4_ploadruht_rr, Convert__Reg1_4__Reg1_2__Reg1_8__Reg1_10__u2_0Imm1_14, AMFBS_None, { MCK_if, MCK__40_, MCK_PredRegs, MCK__41_, MCK_IntRegs, MCK__61_, MCK_memuh, MCK__40_, MCK_IntRegs, MCK__43_, MCK_IntRegs, MCK__LT_, MCK__LT_, MCK__HASH_, MCK_u2_0Imm, MCK__41_ }, },
9789 { 158 /* if */, Hexagon::L2_ploadruhtnew_pi, Convert__Reg1_6__Reg1_10__Reg1_2__Tie1_0_0__s4_1Imm1_14, AMFBS_None, { MCK_if, MCK__40_, MCK_PredRegs, MCK__DOT_, MCK_new, MCK__41_, MCK_IntRegs, MCK__61_, MCK_memuh, MCK__40_, MCK_IntRegs, MCK__43_, MCK__43_, MCK__HASH_, MCK_s4_1Imm, MCK__41_ }, },
9816 { 158 /* if */, Hexagon::L4_ploadruhf_rr, Convert__Reg1_5__Reg1_3__Reg1_9__Reg1_11__u2_0Imm1_15, AMFBS_None, { MCK_if, MCK__40_, MCK__EXCLAIM_, MCK_PredRegs, MCK__41_, MCK_IntRegs, MCK__61_, MCK_memuh, MCK__40_, MCK_IntRegs, MCK__43_, MCK_IntRegs, MCK__LT_, MCK__LT_, MCK__HASH_, MCK_u2_0Imm, MCK__41_ }, },
9834 { 158 /* if */, Hexagon::L2_ploadruhfnew_pi, Convert__Reg1_7__Reg1_11__Reg1_3__Tie1_0_0__s4_1Imm1_15, AMFBS_None, { MCK_if, MCK__40_, MCK__EXCLAIM_, MCK_PredRegs, MCK__DOT_, MCK_new, MCK__41_, MCK_IntRegs, MCK__61_, MCK_memuh, MCK__40_, MCK_IntRegs, MCK__43_, MCK__43_, MCK__HASH_, MCK_s4_1Imm, MCK__41_ }, },
9898 { 158 /* if */, Hexagon::L4_ploadruhtnew_rr, Convert__Reg1_6__Reg1_2__Reg1_10__Reg1_12__u2_0Imm1_16, AMFBS_None, { MCK_if, MCK__40_, MCK_PredRegs, MCK__DOT_, MCK_new, MCK__41_, MCK_IntRegs, MCK__61_, MCK_memuh, MCK__40_, MCK_IntRegs, MCK__43_, MCK_IntRegs, MCK__LT_, MCK__LT_, MCK__HASH_, MCK_u2_0Imm, MCK__41_ }, },
9919 { 158 /* if */, Hexagon::L4_ploadruhfnew_rr, Convert__Reg1_7__Reg1_3__Reg1_11__Reg1_13__u2_0Imm1_17, AMFBS_None, { MCK_if, MCK__40_, MCK__EXCLAIM_, MCK_PredRegs, MCK__DOT_, MCK_new, MCK__41_, MCK_IntRegs, MCK__61_, MCK_memuh, MCK__40_, MCK_IntRegs, MCK__43_, MCK_IntRegs, MCK__LT_, MCK__LT_, MCK__HASH_, MCK_u2_0Imm, MCK__41_ }, },