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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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References
gen/lib/Target/Hexagon/HexagonGenAsmMatcher.inc 4488 return MCK_memubh; // "memubh"
6999 case MCK_memubh: return "MCK_memubh";
7624 { 0 /* */, Hexagon::L2_loadbzw4_io, Convert__Reg1_0__Reg1_4__imm_95_0, AMFBS_None, { MCK_DoubleRegs, MCK__61_, MCK_memubh, MCK__40_, MCK_IntRegs, MCK__41_ }, },
7680 { 0 /* */, Hexagon::L2_loadbzw2_io, Convert__Reg1_0__Reg1_4__imm_95_0, AMFBS_None, { MCK_IntRegs, MCK__61_, MCK_memubh, MCK__40_, MCK_IntRegs, MCK__41_ }, },
8293 { 0 /* */, Hexagon::L2_loadbzw4_io, Convert__Reg1_0__Reg1_4__s30_2Imm1_7, AMFBS_None, { MCK_DoubleRegs, MCK__61_, MCK_memubh, MCK__40_, MCK_IntRegs, MCK__43_, MCK__HASH_, MCK_s30_2Imm, MCK__41_ }, },
8294 { 0 /* */, Hexagon::L2_loadbzw4_pr, Convert__Reg1_0__Reg1_4__Tie1_0_0__Reg1_7, AMFBS_None, { MCK_DoubleRegs, MCK__61_, MCK_memubh, MCK__40_, MCK_IntRegs, MCK__43_, MCK__43_, MCK_ModRegs, MCK__41_ }, },
8295 { 0 /* */, Hexagon::L4_loadbzw4_ap, Convert__Reg1_0__Reg1_4__u32_0Imm1_7, AMFBS_None, { MCK_DoubleRegs, MCK__61_, MCK_memubh, MCK__40_, MCK_IntRegs, MCK__61_, MCK__HASH_, MCK_u32_0Imm, MCK__41_ }, },
8393 { 0 /* */, Hexagon::L2_loadbzw2_io, Convert__Reg1_0__Reg1_4__s31_1Imm1_7, AMFBS_None, { MCK_IntRegs, MCK__61_, MCK_memubh, MCK__40_, MCK_IntRegs, MCK__43_, MCK__HASH_, MCK_s31_1Imm, MCK__41_ }, },
8394 { 0 /* */, Hexagon::L2_loadbzw2_pr, Convert__Reg1_0__Reg1_4__Tie1_0_0__Reg1_7, AMFBS_None, { MCK_IntRegs, MCK__61_, MCK_memubh, MCK__40_, MCK_IntRegs, MCK__43_, MCK__43_, MCK_ModRegs, MCK__41_ }, },
8395 { 0 /* */, Hexagon::L4_loadbzw2_ap, Convert__Reg1_0__Reg1_4__u32_0Imm1_7, AMFBS_None, { MCK_IntRegs, MCK__61_, MCK_memubh, MCK__40_, MCK_IntRegs, MCK__61_, MCK__HASH_, MCK_u32_0Imm, MCK__41_ }, },
8514 { 0 /* */, Hexagon::L2_loadbzw4_pi, Convert__Reg1_0__Reg1_4__Tie1_0_0__s4_2Imm1_8, AMFBS_None, { MCK_DoubleRegs, MCK__61_, MCK_memubh, MCK__40_, MCK_IntRegs, MCK__43_, MCK__43_, MCK__HASH_, MCK_s4_2Imm, MCK__41_ }, },
8543 { 0 /* */, Hexagon::L2_loadbzw2_pi, Convert__Reg1_0__Reg1_4__Tie1_0_0__s4_1Imm1_8, AMFBS_None, { MCK_IntRegs, MCK__61_, MCK_memubh, MCK__40_, MCK_IntRegs, MCK__43_, MCK__43_, MCK__HASH_, MCK_s4_1Imm, MCK__41_ }, },
8595 { 0 /* */, Hexagon::L2_loadbzw4_pbr, Convert__Reg1_0__Reg1_4__Tie1_0_0__Reg1_7, AMFBS_None, { MCK_DoubleRegs, MCK__61_, MCK_memubh, MCK__40_, MCK_IntRegs, MCK__43_, MCK__43_, MCK_ModRegs, MCK__COLON_, MCK_brev, MCK__41_ }, },
8634 { 0 /* */, Hexagon::L2_loadbzw2_pbr, Convert__Reg1_0__Reg1_4__Tie1_0_0__Reg1_7, AMFBS_None, { MCK_IntRegs, MCK__61_, MCK_memubh, MCK__40_, MCK_IntRegs, MCK__43_, MCK__43_, MCK_ModRegs, MCK__COLON_, MCK_brev, MCK__41_ }, },
8767 { 0 /* */, Hexagon::L4_loadbzw4_ur, Convert__Reg1_0__Reg1_4__u2_0Imm1_8__u32_0Imm1_11, AMFBS_None, { MCK_DoubleRegs, MCK__61_, MCK_memubh, MCK__40_, MCK_IntRegs, MCK__LT_, MCK__LT_, MCK__HASH_, MCK_u2_0Imm, MCK__43_, MCK__HASH_, MCK_u32_0Imm, MCK__41_ }, },
8835 { 0 /* */, Hexagon::L4_loadbzw2_ur, Convert__Reg1_0__Reg1_4__u2_0Imm1_8__u32_0Imm1_11, AMFBS_None, { MCK_IntRegs, MCK__61_, MCK_memubh, MCK__40_, MCK_IntRegs, MCK__LT_, MCK__LT_, MCK__HASH_, MCK_u2_0Imm, MCK__43_, MCK__HASH_, MCK_u32_0Imm, MCK__41_ }, },
8986 { 0 /* */, Hexagon::L2_loadbzw4_pcr, Convert__Reg1_0__Reg1_4__Tie1_0_0__Reg1_11, AMFBS_None, { MCK_DoubleRegs, MCK__61_, MCK_memubh, MCK__40_, MCK_IntRegs, MCK__43_, MCK__43_, MCK_I, MCK__COLON_, MCK_circ, MCK__40_, MCK_ModRegs, MCK__41_, MCK__41_ }, },
9029 { 0 /* */, Hexagon::L2_loadbzw2_pcr, Convert__Reg1_0__Reg1_4__Tie1_0_0__Reg1_11, AMFBS_None, { MCK_IntRegs, MCK__61_, MCK_memubh, MCK__40_, MCK_IntRegs, MCK__43_, MCK__43_, MCK_I, MCK__COLON_, MCK_circ, MCK__40_, MCK_ModRegs, MCK__41_, MCK__41_ }, },
9064 { 0 /* */, Hexagon::L2_loadbzw4_pci, Convert__Reg1_0__Reg1_4__Tie1_0_0__s4_2Imm1_8__Reg1_12, AMFBS_None, { MCK_DoubleRegs, MCK__61_, MCK_memubh, MCK__40_, MCK_IntRegs, MCK__43_, MCK__43_, MCK__HASH_, MCK_s4_2Imm, MCK__COLON_, MCK_circ, MCK__40_, MCK_ModRegs, MCK__41_, MCK__41_ }, },
9107 { 0 /* */, Hexagon::L2_loadbzw2_pci, Convert__Reg1_0__Reg1_4__Tie1_0_0__s4_1Imm1_8__Reg1_12, AMFBS_None, { MCK_IntRegs, MCK__61_, MCK_memubh, MCK__40_, MCK_IntRegs, MCK__43_, MCK__43_, MCK__HASH_, MCK_s4_1Imm, MCK__COLON_, MCK_circ, MCK__40_, MCK_ModRegs, MCK__41_, MCK__41_ }, },