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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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References
gen/lib/Target/Hexagon/HexagonGenAsmMatcher.inc 3979 return MCK_membh; // "membh"
6992 case MCK_membh: return "MCK_membh";
7620 { 0 /* */, Hexagon::L2_loadbsw4_io, Convert__Reg1_0__Reg1_4__imm_95_0, AMFBS_None, { MCK_DoubleRegs, MCK__61_, MCK_membh, MCK__40_, MCK_IntRegs, MCK__41_ }, },
7677 { 0 /* */, Hexagon::L2_loadbsw2_io, Convert__Reg1_0__Reg1_4__imm_95_0, AMFBS_None, { MCK_IntRegs, MCK__61_, MCK_membh, MCK__40_, MCK_IntRegs, MCK__41_ }, },
8283 { 0 /* */, Hexagon::L2_loadbsw4_io, Convert__Reg1_0__Reg1_4__s30_2Imm1_7, AMFBS_None, { MCK_DoubleRegs, MCK__61_, MCK_membh, MCK__40_, MCK_IntRegs, MCK__43_, MCK__HASH_, MCK_s30_2Imm, MCK__41_ }, },
8284 { 0 /* */, Hexagon::L2_loadbsw4_pr, Convert__Reg1_0__Reg1_4__Tie1_0_0__Reg1_7, AMFBS_None, { MCK_DoubleRegs, MCK__61_, MCK_membh, MCK__40_, MCK_IntRegs, MCK__43_, MCK__43_, MCK_ModRegs, MCK__41_ }, },
8285 { 0 /* */, Hexagon::L4_loadbsw4_ap, Convert__Reg1_0__Reg1_4__u32_0Imm1_7, AMFBS_None, { MCK_DoubleRegs, MCK__61_, MCK_membh, MCK__40_, MCK_IntRegs, MCK__61_, MCK__HASH_, MCK_u32_0Imm, MCK__41_ }, },
8382 { 0 /* */, Hexagon::L2_loadbsw2_io, Convert__Reg1_0__Reg1_4__s31_1Imm1_7, AMFBS_None, { MCK_IntRegs, MCK__61_, MCK_membh, MCK__40_, MCK_IntRegs, MCK__43_, MCK__HASH_, MCK_s31_1Imm, MCK__41_ }, },
8383 { 0 /* */, Hexagon::L2_loadbsw2_pr, Convert__Reg1_0__Reg1_4__Tie1_0_0__Reg1_7, AMFBS_None, { MCK_IntRegs, MCK__61_, MCK_membh, MCK__40_, MCK_IntRegs, MCK__43_, MCK__43_, MCK_ModRegs, MCK__41_ }, },
8384 { 0 /* */, Hexagon::L4_loadbsw2_ap, Convert__Reg1_0__Reg1_4__u32_0Imm1_7, AMFBS_None, { MCK_IntRegs, MCK__61_, MCK_membh, MCK__40_, MCK_IntRegs, MCK__61_, MCK__HASH_, MCK_u32_0Imm, MCK__41_ }, },
8511 { 0 /* */, Hexagon::L2_loadbsw4_pi, Convert__Reg1_0__Reg1_4__Tie1_0_0__s4_2Imm1_8, AMFBS_None, { MCK_DoubleRegs, MCK__61_, MCK_membh, MCK__40_, MCK_IntRegs, MCK__43_, MCK__43_, MCK__HASH_, MCK_s4_2Imm, MCK__41_ }, },
8540 { 0 /* */, Hexagon::L2_loadbsw2_pi, Convert__Reg1_0__Reg1_4__Tie1_0_0__s4_1Imm1_8, AMFBS_None, { MCK_IntRegs, MCK__61_, MCK_membh, MCK__40_, MCK_IntRegs, MCK__43_, MCK__43_, MCK__HASH_, MCK_s4_1Imm, MCK__41_ }, },
8592 { 0 /* */, Hexagon::L2_loadbsw4_pbr, Convert__Reg1_0__Reg1_4__Tie1_0_0__Reg1_7, AMFBS_None, { MCK_DoubleRegs, MCK__61_, MCK_membh, MCK__40_, MCK_IntRegs, MCK__43_, MCK__43_, MCK_ModRegs, MCK__COLON_, MCK_brev, MCK__41_ }, },
8631 { 0 /* */, Hexagon::L2_loadbsw2_pbr, Convert__Reg1_0__Reg1_4__Tie1_0_0__Reg1_7, AMFBS_None, { MCK_IntRegs, MCK__61_, MCK_membh, MCK__40_, MCK_IntRegs, MCK__43_, MCK__43_, MCK_ModRegs, MCK__COLON_, MCK_brev, MCK__41_ }, },
8764 { 0 /* */, Hexagon::L4_loadbsw4_ur, Convert__Reg1_0__Reg1_4__u2_0Imm1_8__u32_0Imm1_11, AMFBS_None, { MCK_DoubleRegs, MCK__61_, MCK_membh, MCK__40_, MCK_IntRegs, MCK__LT_, MCK__LT_, MCK__HASH_, MCK_u2_0Imm, MCK__43_, MCK__HASH_, MCK_u32_0Imm, MCK__41_ }, },
8832 { 0 /* */, Hexagon::L4_loadbsw2_ur, Convert__Reg1_0__Reg1_4__u2_0Imm1_8__u32_0Imm1_11, AMFBS_None, { MCK_IntRegs, MCK__61_, MCK_membh, MCK__40_, MCK_IntRegs, MCK__LT_, MCK__LT_, MCK__HASH_, MCK_u2_0Imm, MCK__43_, MCK__HASH_, MCK_u32_0Imm, MCK__41_ }, },
8983 { 0 /* */, Hexagon::L2_loadbsw4_pcr, Convert__Reg1_0__Reg1_4__Tie1_0_0__Reg1_11, AMFBS_None, { MCK_DoubleRegs, MCK__61_, MCK_membh, MCK__40_, MCK_IntRegs, MCK__43_, MCK__43_, MCK_I, MCK__COLON_, MCK_circ, MCK__40_, MCK_ModRegs, MCK__41_, MCK__41_ }, },
9026 { 0 /* */, Hexagon::L2_loadbsw2_pcr, Convert__Reg1_0__Reg1_4__Tie1_0_0__Reg1_11, AMFBS_None, { MCK_IntRegs, MCK__61_, MCK_membh, MCK__40_, MCK_IntRegs, MCK__43_, MCK__43_, MCK_I, MCK__COLON_, MCK_circ, MCK__40_, MCK_ModRegs, MCK__41_, MCK__41_ }, },
9061 { 0 /* */, Hexagon::L2_loadbsw4_pci, Convert__Reg1_0__Reg1_4__Tie1_0_0__s4_2Imm1_8__Reg1_12, AMFBS_None, { MCK_DoubleRegs, MCK__61_, MCK_membh, MCK__40_, MCK_IntRegs, MCK__43_, MCK__43_, MCK__HASH_, MCK_s4_2Imm, MCK__COLON_, MCK_circ, MCK__40_, MCK_ModRegs, MCK__41_, MCK__41_ }, },
9104 { 0 /* */, Hexagon::L2_loadbsw2_pci, Convert__Reg1_0__Reg1_4__Tie1_0_0__s4_1Imm1_8__Reg1_12, AMFBS_None, { MCK_IntRegs, MCK__61_, MCK_membh, MCK__40_, MCK_IntRegs, MCK__43_, MCK__43_, MCK__HASH_, MCK_s4_1Imm, MCK__COLON_, MCK_circ, MCK__40_, MCK_ModRegs, MCK__41_, MCK__41_ }, },