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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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References
gen/lib/Target/Hexagon/HexagonGenAsmMatcher.inc 3500 return MCK_lsl; // "lsl"
6983 case MCK_lsl: return "MCK_lsl";
7759 { 0 /* */, Hexagon::S2_lsl_r_p, Convert__Reg1_0__Reg1_4__Reg1_5, AMFBS_None, { MCK_DoubleRegs, MCK__61_, MCK_lsl, MCK__40_, MCK_DoubleRegs, MCK_IntRegs, MCK__41_ }, },
7894 { 0 /* */, Hexagon::S2_lsl_r_r, Convert__Reg1_0__Reg1_4__Reg1_5, AMFBS_None, { MCK_IntRegs, MCK__61_, MCK_lsl, MCK__40_, MCK_IntRegs, MCK_IntRegs, MCK__41_ }, },
8029 { 0 /* */, Hexagon::S2_lsl_r_p_and, Convert__Reg1_0__Tie0_0_0__Reg1_5__Reg1_6, AMFBS_None, { MCK_DoubleRegs, MCK__38_, MCK__61_, MCK_lsl, MCK__40_, MCK_DoubleRegs, MCK_IntRegs, MCK__41_ }, },
8035 { 0 /* */, Hexagon::S2_lsl_r_p_acc, Convert__Reg1_0__Tie0_0_0__Reg1_5__Reg1_6, AMFBS_None, { MCK_DoubleRegs, MCK__43_, MCK__61_, MCK_lsl, MCK__40_, MCK_DoubleRegs, MCK_IntRegs, MCK__41_ }, },
8055 { 0 /* */, Hexagon::S2_lsl_r_p_nac, Convert__Reg1_0__Tie0_0_0__Reg1_5__Reg1_6, AMFBS_None, { MCK_DoubleRegs, MCK__MINUS_, MCK__61_, MCK_lsl, MCK__40_, MCK_DoubleRegs, MCK_IntRegs, MCK__41_ }, },
8091 { 0 /* */, Hexagon::S2_lsl_r_p_xor, Convert__Reg1_0__Tie0_0_0__Reg1_5__Reg1_6, AMFBS_None, { MCK_DoubleRegs, MCK__94_, MCK__61_, MCK_lsl, MCK__40_, MCK_DoubleRegs, MCK_IntRegs, MCK__41_ }, },
8098 { 0 /* */, Hexagon::S2_lsl_r_p_or, Convert__Reg1_0__Tie0_0_0__Reg1_5__Reg1_6, AMFBS_None, { MCK_DoubleRegs, MCK__124_, MCK__61_, MCK_lsl, MCK__40_, MCK_DoubleRegs, MCK_IntRegs, MCK__41_ }, },
8131 { 0 /* */, Hexagon::S2_lsl_r_r_and, Convert__Reg1_0__Tie0_0_0__Reg1_5__Reg1_6, AMFBS_None, { MCK_IntRegs, MCK__38_, MCK__61_, MCK_lsl, MCK__40_, MCK_IntRegs, MCK_IntRegs, MCK__41_ }, },
8138 { 0 /* */, Hexagon::S2_lsl_r_r_acc, Convert__Reg1_0__Tie0_0_0__Reg1_5__Reg1_6, AMFBS_None, { MCK_IntRegs, MCK__43_, MCK__61_, MCK_lsl, MCK__40_, MCK_IntRegs, MCK_IntRegs, MCK__41_ }, },
8146 { 0 /* */, Hexagon::S2_lsl_r_r_nac, Convert__Reg1_0__Tie0_0_0__Reg1_5__Reg1_6, AMFBS_None, { MCK_IntRegs, MCK__MINUS_, MCK__61_, MCK_lsl, MCK__40_, MCK_IntRegs, MCK_IntRegs, MCK__41_ }, },
8164 { 0 /* */, Hexagon::S4_lsli, Convert__Reg1_0__s6_0Imm1_5__Reg1_6, AMFBS_None, { MCK_IntRegs, MCK__61_, MCK_lsl, MCK__40_, MCK__HASH_, MCK_s6_0Imm, MCK_IntRegs, MCK__41_ }, },
8185 { 0 /* */, Hexagon::S2_lsl_r_r_or, Convert__Reg1_0__Tie0_0_0__Reg1_5__Reg1_6, AMFBS_None, { MCK_IntRegs, MCK__124_, MCK__61_, MCK_lsl, MCK__40_, MCK_IntRegs, MCK_IntRegs, MCK__41_ }, },