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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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References
gen/lib/Target/Hexagon/HexagonGenAsmMatcher.inc 3650 return MCK_circ; // "circ"
6901 case MCK_circ: return "MCK_circ";
8982 { 0 /* */, Hexagon::L2_loadalignb_pcr, Convert__Reg1_0__Reg1_4__Tie0_0_0__Tie1_0_0__Reg1_11, AMFBS_None, { MCK_DoubleRegs, MCK__61_, MCK_memb_95_fifo, MCK__40_, MCK_IntRegs, MCK__43_, MCK__43_, MCK_I, MCK__COLON_, MCK_circ, MCK__40_, MCK_ModRegs, MCK__41_, MCK__41_ }, },
8983 { 0 /* */, Hexagon::L2_loadbsw4_pcr, Convert__Reg1_0__Reg1_4__Tie1_0_0__Reg1_11, AMFBS_None, { MCK_DoubleRegs, MCK__61_, MCK_membh, MCK__40_, MCK_IntRegs, MCK__43_, MCK__43_, MCK_I, MCK__COLON_, MCK_circ, MCK__40_, MCK_ModRegs, MCK__41_, MCK__41_ }, },
8984 { 0 /* */, Hexagon::L2_loadrd_pcr, Convert__Reg1_0__Reg1_4__Tie1_0_0__Reg1_11, AMFBS_None, { MCK_DoubleRegs, MCK__61_, MCK_memd, MCK__40_, MCK_IntRegs, MCK__43_, MCK__43_, MCK_I, MCK__COLON_, MCK_circ, MCK__40_, MCK_ModRegs, MCK__41_, MCK__41_ }, },
8985 { 0 /* */, Hexagon::L2_loadalignh_pcr, Convert__Reg1_0__Reg1_4__Tie0_0_0__Tie1_0_0__Reg1_11, AMFBS_None, { MCK_DoubleRegs, MCK__61_, MCK_memh_95_fifo, MCK__40_, MCK_IntRegs, MCK__43_, MCK__43_, MCK_I, MCK__COLON_, MCK_circ, MCK__40_, MCK_ModRegs, MCK__41_, MCK__41_ }, },
8986 { 0 /* */, Hexagon::L2_loadbzw4_pcr, Convert__Reg1_0__Reg1_4__Tie1_0_0__Reg1_11, AMFBS_None, { MCK_DoubleRegs, MCK__61_, MCK_memubh, MCK__40_, MCK_IntRegs, MCK__43_, MCK__43_, MCK_I, MCK__COLON_, MCK_circ, MCK__40_, MCK_ModRegs, MCK__41_, MCK__41_ }, },
9025 { 0 /* */, Hexagon::L2_loadrb_pcr, Convert__Reg1_0__Reg1_4__Tie1_0_0__Reg1_11, AMFBS_None, { MCK_IntRegs, MCK__61_, MCK_memb, MCK__40_, MCK_IntRegs, MCK__43_, MCK__43_, MCK_I, MCK__COLON_, MCK_circ, MCK__40_, MCK_ModRegs, MCK__41_, MCK__41_ }, },
9026 { 0 /* */, Hexagon::L2_loadbsw2_pcr, Convert__Reg1_0__Reg1_4__Tie1_0_0__Reg1_11, AMFBS_None, { MCK_IntRegs, MCK__61_, MCK_membh, MCK__40_, MCK_IntRegs, MCK__43_, MCK__43_, MCK_I, MCK__COLON_, MCK_circ, MCK__40_, MCK_ModRegs, MCK__41_, MCK__41_ }, },
9027 { 0 /* */, Hexagon::L2_loadrh_pcr, Convert__Reg1_0__Reg1_4__Tie1_0_0__Reg1_11, AMFBS_None, { MCK_IntRegs, MCK__61_, MCK_memh, MCK__40_, MCK_IntRegs, MCK__43_, MCK__43_, MCK_I, MCK__COLON_, MCK_circ, MCK__40_, MCK_ModRegs, MCK__41_, MCK__41_ }, },
9028 { 0 /* */, Hexagon::L2_loadrub_pcr, Convert__Reg1_0__Reg1_4__Tie1_0_0__Reg1_11, AMFBS_None, { MCK_IntRegs, MCK__61_, MCK_memub, MCK__40_, MCK_IntRegs, MCK__43_, MCK__43_, MCK_I, MCK__COLON_, MCK_circ, MCK__40_, MCK_ModRegs, MCK__41_, MCK__41_ }, },
9029 { 0 /* */, Hexagon::L2_loadbzw2_pcr, Convert__Reg1_0__Reg1_4__Tie1_0_0__Reg1_11, AMFBS_None, { MCK_IntRegs, MCK__61_, MCK_memubh, MCK__40_, MCK_IntRegs, MCK__43_, MCK__43_, MCK_I, MCK__COLON_, MCK_circ, MCK__40_, MCK_ModRegs, MCK__41_, MCK__41_ }, },
9030 { 0 /* */, Hexagon::L2_loadruh_pcr, Convert__Reg1_0__Reg1_4__Tie1_0_0__Reg1_11, AMFBS_None, { MCK_IntRegs, MCK__61_, MCK_memuh, MCK__40_, MCK_IntRegs, MCK__43_, MCK__43_, MCK_I, MCK__COLON_, MCK_circ, MCK__40_, MCK_ModRegs, MCK__41_, MCK__41_ }, },
9031 { 0 /* */, Hexagon::L2_loadri_pcr, Convert__Reg1_0__Reg1_4__Tie1_0_0__Reg1_11, AMFBS_None, { MCK_IntRegs, MCK__61_, MCK_memw, MCK__40_, MCK_IntRegs, MCK__43_, MCK__43_, MCK_I, MCK__COLON_, MCK_circ, MCK__40_, MCK_ModRegs, MCK__41_, MCK__41_ }, },
9060 { 0 /* */, Hexagon::L2_loadalignb_pci, Convert__Reg1_0__Reg1_4__Tie0_0_0__Tie1_0_0__s4_0Imm1_8__Reg1_12, AMFBS_None, { MCK_DoubleRegs, MCK__61_, MCK_memb_95_fifo, MCK__40_, MCK_IntRegs, MCK__43_, MCK__43_, MCK__HASH_, MCK_s4_0Imm, MCK__COLON_, MCK_circ, MCK__40_, MCK_ModRegs, MCK__41_, MCK__41_ }, },
9061 { 0 /* */, Hexagon::L2_loadbsw4_pci, Convert__Reg1_0__Reg1_4__Tie1_0_0__s4_2Imm1_8__Reg1_12, AMFBS_None, { MCK_DoubleRegs, MCK__61_, MCK_membh, MCK__40_, MCK_IntRegs, MCK__43_, MCK__43_, MCK__HASH_, MCK_s4_2Imm, MCK__COLON_, MCK_circ, MCK__40_, MCK_ModRegs, MCK__41_, MCK__41_ }, },
9062 { 0 /* */, Hexagon::L2_loadrd_pci, Convert__Reg1_0__Reg1_4__Tie1_0_0__s4_3Imm1_8__Reg1_12, AMFBS_None, { MCK_DoubleRegs, MCK__61_, MCK_memd, MCK__40_, MCK_IntRegs, MCK__43_, MCK__43_, MCK__HASH_, MCK_s4_3Imm, MCK__COLON_, MCK_circ, MCK__40_, MCK_ModRegs, MCK__41_, MCK__41_ }, },
9063 { 0 /* */, Hexagon::L2_loadalignh_pci, Convert__Reg1_0__Reg1_4__Tie0_0_0__Tie1_0_0__s4_1Imm1_8__Reg1_12, AMFBS_None, { MCK_DoubleRegs, MCK__61_, MCK_memh_95_fifo, MCK__40_, MCK_IntRegs, MCK__43_, MCK__43_, MCK__HASH_, MCK_s4_1Imm, MCK__COLON_, MCK_circ, MCK__40_, MCK_ModRegs, MCK__41_, MCK__41_ }, },
9064 { 0 /* */, Hexagon::L2_loadbzw4_pci, Convert__Reg1_0__Reg1_4__Tie1_0_0__s4_2Imm1_8__Reg1_12, AMFBS_None, { MCK_DoubleRegs, MCK__61_, MCK_memubh, MCK__40_, MCK_IntRegs, MCK__43_, MCK__43_, MCK__HASH_, MCK_s4_2Imm, MCK__COLON_, MCK_circ, MCK__40_, MCK_ModRegs, MCK__41_, MCK__41_ }, },
9103 { 0 /* */, Hexagon::L2_loadrb_pci, Convert__Reg1_0__Reg1_4__Tie1_0_0__s4_0Imm1_8__Reg1_12, AMFBS_None, { MCK_IntRegs, MCK__61_, MCK_memb, MCK__40_, MCK_IntRegs, MCK__43_, MCK__43_, MCK__HASH_, MCK_s4_0Imm, MCK__COLON_, MCK_circ, MCK__40_, MCK_ModRegs, MCK__41_, MCK__41_ }, },
9104 { 0 /* */, Hexagon::L2_loadbsw2_pci, Convert__Reg1_0__Reg1_4__Tie1_0_0__s4_1Imm1_8__Reg1_12, AMFBS_None, { MCK_IntRegs, MCK__61_, MCK_membh, MCK__40_, MCK_IntRegs, MCK__43_, MCK__43_, MCK__HASH_, MCK_s4_1Imm, MCK__COLON_, MCK_circ, MCK__40_, MCK_ModRegs, MCK__41_, MCK__41_ }, },
9105 { 0 /* */, Hexagon::L2_loadrh_pci, Convert__Reg1_0__Reg1_4__Tie1_0_0__s4_1Imm1_8__Reg1_12, AMFBS_None, { MCK_IntRegs, MCK__61_, MCK_memh, MCK__40_, MCK_IntRegs, MCK__43_, MCK__43_, MCK__HASH_, MCK_s4_1Imm, MCK__COLON_, MCK_circ, MCK__40_, MCK_ModRegs, MCK__41_, MCK__41_ }, },
9106 { 0 /* */, Hexagon::L2_loadrub_pci, Convert__Reg1_0__Reg1_4__Tie1_0_0__s4_0Imm1_8__Reg1_12, AMFBS_None, { MCK_IntRegs, MCK__61_, MCK_memub, MCK__40_, MCK_IntRegs, MCK__43_, MCK__43_, MCK__HASH_, MCK_s4_0Imm, MCK__COLON_, MCK_circ, MCK__40_, MCK_ModRegs, MCK__41_, MCK__41_ }, },
9107 { 0 /* */, Hexagon::L2_loadbzw2_pci, Convert__Reg1_0__Reg1_4__Tie1_0_0__s4_1Imm1_8__Reg1_12, AMFBS_None, { MCK_IntRegs, MCK__61_, MCK_memubh, MCK__40_, MCK_IntRegs, MCK__43_, MCK__43_, MCK__HASH_, MCK_s4_1Imm, MCK__COLON_, MCK_circ, MCK__40_, MCK_ModRegs, MCK__41_, MCK__41_ }, },
9108 { 0 /* */, Hexagon::L2_loadruh_pci, Convert__Reg1_0__Reg1_4__Tie1_0_0__s4_1Imm1_8__Reg1_12, AMFBS_None, { MCK_IntRegs, MCK__61_, MCK_memuh, MCK__40_, MCK_IntRegs, MCK__43_, MCK__43_, MCK__HASH_, MCK_s4_1Imm, MCK__COLON_, MCK_circ, MCK__40_, MCK_ModRegs, MCK__41_, MCK__41_ }, },
9109 { 0 /* */, Hexagon::L2_loadri_pci, Convert__Reg1_0__Reg1_4__Tie1_0_0__s4_2Imm1_8__Reg1_12, AMFBS_None, { MCK_IntRegs, MCK__61_, MCK_memw, MCK__40_, MCK_IntRegs, MCK__43_, MCK__43_, MCK__HASH_, MCK_s4_2Imm, MCK__COLON_, MCK_circ, MCK__40_, MCK_ModRegs, MCK__41_, MCK__41_ }, },
9979 { 205 /* memb */, Hexagon::S2_storerb_pcr, Convert__Reg1_2__Tie0_0_0__Reg1_9__Reg1_13, AMFBS_None, { MCK_memb, MCK__40_, MCK_IntRegs, MCK__43_, MCK__43_, MCK_I, MCK__COLON_, MCK_circ, MCK__40_, MCK_ModRegs, MCK__41_, MCK__41_, MCK__61_, MCK_IntRegs }, },
9981 { 205 /* memb */, Hexagon::S2_storerb_pci, Convert__Reg1_2__Tie0_0_0__s4_0Imm1_6__Reg1_10__Reg1_14, AMFBS_None, { MCK_memb, MCK__40_, MCK_IntRegs, MCK__43_, MCK__43_, MCK__HASH_, MCK_s4_0Imm, MCK__COLON_, MCK_circ, MCK__40_, MCK_ModRegs, MCK__41_, MCK__41_, MCK__61_, MCK_IntRegs }, },
9983 { 205 /* memb */, Hexagon::S2_storerbnew_pcr, Convert__Reg1_2__Tie0_0_0__Reg1_9__Reg1_13, AMFBS_None, { MCK_memb, MCK__40_, MCK_IntRegs, MCK__43_, MCK__43_, MCK_I, MCK__COLON_, MCK_circ, MCK__40_, MCK_ModRegs, MCK__41_, MCK__41_, MCK__61_, MCK_IntRegs, MCK__DOT_, MCK_new }, },
9984 { 205 /* memb */, Hexagon::S2_storerbnew_pci, Convert__Reg1_2__Tie0_0_0__s4_0Imm1_6__Reg1_10__Reg1_14, AMFBS_None, { MCK_memb, MCK__40_, MCK_IntRegs, MCK__43_, MCK__43_, MCK__HASH_, MCK_s4_0Imm, MCK__COLON_, MCK_circ, MCK__40_, MCK_ModRegs, MCK__41_, MCK__41_, MCK__61_, MCK_IntRegs, MCK__DOT_, MCK_new }, },
9996 { 217 /* memd */, Hexagon::S2_storerd_pcr, Convert__Reg1_2__Tie0_0_0__Reg1_9__Reg1_13, AMFBS_None, { MCK_memd, MCK__40_, MCK_IntRegs, MCK__43_, MCK__43_, MCK_I, MCK__COLON_, MCK_circ, MCK__40_, MCK_ModRegs, MCK__41_, MCK__41_, MCK__61_, MCK_DoubleRegs }, },
9997 { 217 /* memd */, Hexagon::S2_storerd_pci, Convert__Reg1_2__Tie0_0_0__s4_3Imm1_6__Reg1_10__Reg1_14, AMFBS_None, { MCK_memd, MCK__40_, MCK_IntRegs, MCK__43_, MCK__43_, MCK__HASH_, MCK_s4_3Imm, MCK__COLON_, MCK_circ, MCK__40_, MCK_ModRegs, MCK__41_, MCK__41_, MCK__61_, MCK_DoubleRegs }, },
10043 { 234 /* memh */, Hexagon::S2_storerh_pcr, Convert__Reg1_2__Tie0_0_0__Reg1_9__Reg1_13, AMFBS_None, { MCK_memh, MCK__40_, MCK_IntRegs, MCK__43_, MCK__43_, MCK_I, MCK__COLON_, MCK_circ, MCK__40_, MCK_ModRegs, MCK__41_, MCK__41_, MCK__61_, MCK_IntRegs }, },
10046 { 234 /* memh */, Hexagon::S2_storerh_pci, Convert__Reg1_2__Tie0_0_0__s4_1Imm1_6__Reg1_10__Reg1_14, AMFBS_None, { MCK_memh, MCK__40_, MCK_IntRegs, MCK__43_, MCK__43_, MCK__HASH_, MCK_s4_1Imm, MCK__COLON_, MCK_circ, MCK__40_, MCK_ModRegs, MCK__41_, MCK__41_, MCK__61_, MCK_IntRegs }, },
10049 { 234 /* memh */, Hexagon::S2_storerf_pcr, Convert__Reg1_2__Tie0_0_0__Reg1_9__Reg1_13, AMFBS_None, { MCK_memh, MCK__40_, MCK_IntRegs, MCK__43_, MCK__43_, MCK_I, MCK__COLON_, MCK_circ, MCK__40_, MCK_ModRegs, MCK__41_, MCK__41_, MCK__61_, MCK_IntRegs, MCK__DOT_, MCK_h }, },
10050 { 234 /* memh */, Hexagon::S2_storerhnew_pcr, Convert__Reg1_2__Tie0_0_0__Reg1_9__Reg1_13, AMFBS_None, { MCK_memh, MCK__40_, MCK_IntRegs, MCK__43_, MCK__43_, MCK_I, MCK__COLON_, MCK_circ, MCK__40_, MCK_ModRegs, MCK__41_, MCK__41_, MCK__61_, MCK_IntRegs, MCK__DOT_, MCK_new }, },
10051 { 234 /* memh */, Hexagon::S2_storerf_pci, Convert__Reg1_2__Tie0_0_0__s4_1Imm1_6__Reg1_10__Reg1_14, AMFBS_None, { MCK_memh, MCK__40_, MCK_IntRegs, MCK__43_, MCK__43_, MCK__HASH_, MCK_s4_1Imm, MCK__COLON_, MCK_circ, MCK__40_, MCK_ModRegs, MCK__41_, MCK__41_, MCK__61_, MCK_IntRegs, MCK__DOT_, MCK_h }, },
10052 { 234 /* memh */, Hexagon::S2_storerhnew_pci, Convert__Reg1_2__Tie0_0_0__s4_1Imm1_6__Reg1_10__Reg1_14, AMFBS_None, { MCK_memh, MCK__40_, MCK_IntRegs, MCK__43_, MCK__43_, MCK__HASH_, MCK_s4_1Imm, MCK__COLON_, MCK_circ, MCK__40_, MCK_ModRegs, MCK__41_, MCK__41_, MCK__61_, MCK_IntRegs, MCK__DOT_, MCK_new }, },
10089 { 239 /* memw */, Hexagon::S2_storeri_pcr, Convert__Reg1_2__Tie0_0_0__Reg1_9__Reg1_13, AMFBS_None, { MCK_memw, MCK__40_, MCK_IntRegs, MCK__43_, MCK__43_, MCK_I, MCK__COLON_, MCK_circ, MCK__40_, MCK_ModRegs, MCK__41_, MCK__41_, MCK__61_, MCK_IntRegs }, },
10091 { 239 /* memw */, Hexagon::S2_storeri_pci, Convert__Reg1_2__Tie0_0_0__s4_2Imm1_6__Reg1_10__Reg1_14, AMFBS_None, { MCK_memw, MCK__40_, MCK_IntRegs, MCK__43_, MCK__43_, MCK__HASH_, MCK_s4_2Imm, MCK__COLON_, MCK_circ, MCK__40_, MCK_ModRegs, MCK__41_, MCK__41_, MCK__61_, MCK_IntRegs }, },
10093 { 239 /* memw */, Hexagon::S2_storerinew_pcr, Convert__Reg1_2__Tie0_0_0__Reg1_9__Reg1_13, AMFBS_None, { MCK_memw, MCK__40_, MCK_IntRegs, MCK__43_, MCK__43_, MCK_I, MCK__COLON_, MCK_circ, MCK__40_, MCK_ModRegs, MCK__41_, MCK__41_, MCK__61_, MCK_IntRegs, MCK__DOT_, MCK_new }, },
10094 { 239 /* memw */, Hexagon::S2_storerinew_pci, Convert__Reg1_2__Tie0_0_0__s4_2Imm1_6__Reg1_10__Reg1_14, AMFBS_None, { MCK_memw, MCK__40_, MCK_IntRegs, MCK__43_, MCK__43_, MCK__HASH_, MCK_s4_2Imm, MCK__COLON_, MCK_circ, MCK__40_, MCK_ModRegs, MCK__41_, MCK__41_, MCK__61_, MCK_IntRegs, MCK__DOT_, MCK_new }, },