|
|
reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
|
References
gen/lib/Target/Hexagon/HexagonGenAsmMatcher.inc 3297 return MCK__38_; // "&"
6856 case MCK__38_: return "MCK__38_";
8027 { 0 /* */, Hexagon::S2_asl_r_p_and, Convert__Reg1_0__Tie0_0_0__Reg1_5__Reg1_6, AMFBS_None, { MCK_DoubleRegs, MCK__38_, MCK__61_, MCK_asl, MCK__40_, MCK_DoubleRegs, MCK_IntRegs, MCK__41_ }, },
8028 { 0 /* */, Hexagon::S2_asr_r_p_and, Convert__Reg1_0__Tie0_0_0__Reg1_5__Reg1_6, AMFBS_None, { MCK_DoubleRegs, MCK__38_, MCK__61_, MCK_asr, MCK__40_, MCK_DoubleRegs, MCK_IntRegs, MCK__41_ }, },
8029 { 0 /* */, Hexagon::S2_lsl_r_p_and, Convert__Reg1_0__Tie0_0_0__Reg1_5__Reg1_6, AMFBS_None, { MCK_DoubleRegs, MCK__38_, MCK__61_, MCK_lsl, MCK__40_, MCK_DoubleRegs, MCK_IntRegs, MCK__41_ }, },
8030 { 0 /* */, Hexagon::S2_lsr_r_p_and, Convert__Reg1_0__Tie0_0_0__Reg1_5__Reg1_6, AMFBS_None, { MCK_DoubleRegs, MCK__38_, MCK__61_, MCK_lsr, MCK__40_, MCK_DoubleRegs, MCK_IntRegs, MCK__41_ }, },
8128 { 0 /* */, Hexagon::M4_and_and, Convert__Reg1_0__Tie0_0_0__Reg1_5__Reg1_6, AMFBS_None, { MCK_IntRegs, MCK__38_, MCK__61_, MCK_and, MCK__40_, MCK_IntRegs, MCK_IntRegs, MCK__41_ }, },
8129 { 0 /* */, Hexagon::S2_asl_r_r_and, Convert__Reg1_0__Tie0_0_0__Reg1_5__Reg1_6, AMFBS_None, { MCK_IntRegs, MCK__38_, MCK__61_, MCK_asl, MCK__40_, MCK_IntRegs, MCK_IntRegs, MCK__41_ }, },
8130 { 0 /* */, Hexagon::S2_asr_r_r_and, Convert__Reg1_0__Tie0_0_0__Reg1_5__Reg1_6, AMFBS_None, { MCK_IntRegs, MCK__38_, MCK__61_, MCK_asr, MCK__40_, MCK_IntRegs, MCK_IntRegs, MCK__41_ }, },
8131 { 0 /* */, Hexagon::S2_lsl_r_r_and, Convert__Reg1_0__Tie0_0_0__Reg1_5__Reg1_6, AMFBS_None, { MCK_IntRegs, MCK__38_, MCK__61_, MCK_lsl, MCK__40_, MCK_IntRegs, MCK_IntRegs, MCK__41_ }, },
8132 { 0 /* */, Hexagon::S2_lsr_r_r_and, Convert__Reg1_0__Tie0_0_0__Reg1_5__Reg1_6, AMFBS_None, { MCK_IntRegs, MCK__38_, MCK__61_, MCK_lsr, MCK__40_, MCK_IntRegs, MCK_IntRegs, MCK__41_ }, },
8133 { 0 /* */, Hexagon::M4_and_or, Convert__Reg1_0__Tie0_0_0__Reg1_5__Reg1_6, AMFBS_None, { MCK_IntRegs, MCK__38_, MCK__61_, MCK_or, MCK__40_, MCK_IntRegs, MCK_IntRegs, MCK__41_ }, },
8134 { 0 /* */, Hexagon::M4_and_xor, Convert__Reg1_0__Tie0_0_0__Reg1_5__Reg1_6, AMFBS_None, { MCK_IntRegs, MCK__38_, MCK__61_, MCK_xor, MCK__40_, MCK_IntRegs, MCK_IntRegs, MCK__41_ }, },
8259 { 0 /* */, Hexagon::S2_asl_i_p_and, Convert__Reg1_0__Tie0_0_0__Reg1_5__u6_0Imm1_7, AMFBS_None, { MCK_DoubleRegs, MCK__38_, MCK__61_, MCK_asl, MCK__40_, MCK_DoubleRegs, MCK__HASH_, MCK_u6_0Imm, MCK__41_ }, },
8260 { 0 /* */, Hexagon::S2_asr_i_p_and, Convert__Reg1_0__Tie0_0_0__Reg1_5__u6_0Imm1_7, AMFBS_None, { MCK_DoubleRegs, MCK__38_, MCK__61_, MCK_asr, MCK__40_, MCK_DoubleRegs, MCK__HASH_, MCK_u6_0Imm, MCK__41_ }, },
8261 { 0 /* */, Hexagon::S2_lsr_i_p_and, Convert__Reg1_0__Tie0_0_0__Reg1_5__u6_0Imm1_7, AMFBS_None, { MCK_DoubleRegs, MCK__38_, MCK__61_, MCK_lsr, MCK__40_, MCK_DoubleRegs, MCK__HASH_, MCK_u6_0Imm, MCK__41_ }, },
8262 { 0 /* */, Hexagon::S6_rol_i_p_and, Convert__Reg1_0__Tie0_0_0__Reg1_5__u6_0Imm1_7, AMFBS_HasV60, { MCK_DoubleRegs, MCK__38_, MCK__61_, MCK_rol, MCK__40_, MCK_DoubleRegs, MCK__HASH_, MCK_u6_0Imm, MCK__41_ }, },
8352 { 0 /* */, Hexagon::M4_and_andn, Convert__Reg1_0__Tie0_0_0__Reg1_5__Reg1_7, AMFBS_None, { MCK_IntRegs, MCK__38_, MCK__61_, MCK_and, MCK__40_, MCK_IntRegs, MCK__126_, MCK_IntRegs, MCK__41_ }, },
8353 { 0 /* */, Hexagon::S2_asl_i_r_and, Convert__Reg1_0__Tie0_0_0__Reg1_5__u5_0Imm1_7, AMFBS_None, { MCK_IntRegs, MCK__38_, MCK__61_, MCK_asl, MCK__40_, MCK_IntRegs, MCK__HASH_, MCK_u5_0Imm, MCK__41_ }, },
8354 { 0 /* */, Hexagon::S2_asr_i_r_and, Convert__Reg1_0__Tie0_0_0__Reg1_5__u5_0Imm1_7, AMFBS_None, { MCK_IntRegs, MCK__38_, MCK__61_, MCK_asr, MCK__40_, MCK_IntRegs, MCK__HASH_, MCK_u5_0Imm, MCK__41_ }, },
8355 { 0 /* */, Hexagon::S2_lsr_i_r_and, Convert__Reg1_0__Tie0_0_0__Reg1_5__u5_0Imm1_7, AMFBS_None, { MCK_IntRegs, MCK__38_, MCK__61_, MCK_lsr, MCK__40_, MCK_IntRegs, MCK__HASH_, MCK_u5_0Imm, MCK__41_ }, },
8356 { 0 /* */, Hexagon::S6_rol_i_r_and, Convert__Reg1_0__Tie0_0_0__Reg1_5__u5_0Imm1_7, AMFBS_HasV60, { MCK_IntRegs, MCK__38_, MCK__61_, MCK_rol, MCK__40_, MCK_IntRegs, MCK__HASH_, MCK_u5_0Imm, MCK__41_ }, },
8928 { 0 /* */, Hexagon::V6_veqb_and, Convert__Reg1_0__Tie0_0_0__Reg1_7__Reg1_10, AMFBS_UseHVXV60, { MCK_HvxQR, MCK__38_, MCK__61_, MCK_vcmp, MCK__DOT_, MCK_eq, MCK__40_, MCK_HvxVR, MCK__DOT_, MCK_b, MCK_HvxVR, MCK__DOT_, MCK_b, MCK__41_ }, },
8929 { 0 /* */, Hexagon::V6_veqh_and, Convert__Reg1_0__Tie0_0_0__Reg1_7__Reg1_10, AMFBS_UseHVXV60, { MCK_HvxQR, MCK__38_, MCK__61_, MCK_vcmp, MCK__DOT_, MCK_eq, MCK__40_, MCK_HvxVR, MCK__DOT_, MCK_h, MCK_HvxVR, MCK__DOT_, MCK_h, MCK__41_ }, },
8930 { 0 /* */, Hexagon::V6_veqb_and, Convert__Reg1_0__Tie0_0_0__Reg1_7__Reg1_10, AMFBS_UseHVX, { MCK_HvxQR, MCK__38_, MCK__61_, MCK_vcmp, MCK__DOT_, MCK_eq, MCK__40_, MCK_HvxVR, MCK__DOT_, MCK_ub, MCK_HvxVR, MCK__DOT_, MCK_ub, MCK__41_ }, },
8931 { 0 /* */, Hexagon::V6_veqh_and, Convert__Reg1_0__Tie0_0_0__Reg1_7__Reg1_10, AMFBS_UseHVX, { MCK_HvxQR, MCK__38_, MCK__61_, MCK_vcmp, MCK__DOT_, MCK_eq, MCK__40_, MCK_HvxVR, MCK__DOT_, MCK_uh, MCK_HvxVR, MCK__DOT_, MCK_uh, MCK__41_ }, },
8932 { 0 /* */, Hexagon::V6_veqw_and, Convert__Reg1_0__Tie0_0_0__Reg1_7__Reg1_10, AMFBS_UseHVX, { MCK_HvxQR, MCK__38_, MCK__61_, MCK_vcmp, MCK__DOT_, MCK_eq, MCK__40_, MCK_HvxVR, MCK__DOT_, MCK_uw, MCK_HvxVR, MCK__DOT_, MCK_uw, MCK__41_ }, },
8933 { 0 /* */, Hexagon::V6_veqw_and, Convert__Reg1_0__Tie0_0_0__Reg1_7__Reg1_10, AMFBS_UseHVXV60, { MCK_HvxQR, MCK__38_, MCK__61_, MCK_vcmp, MCK__DOT_, MCK_eq, MCK__40_, MCK_HvxVR, MCK__DOT_, MCK_w, MCK_HvxVR, MCK__DOT_, MCK_w, MCK__41_ }, },
8934 { 0 /* */, Hexagon::V6_vgtb_and, Convert__Reg1_0__Tie0_0_0__Reg1_7__Reg1_10, AMFBS_UseHVXV60, { MCK_HvxQR, MCK__38_, MCK__61_, MCK_vcmp, MCK__DOT_, MCK_gt, MCK__40_, MCK_HvxVR, MCK__DOT_, MCK_b, MCK_HvxVR, MCK__DOT_, MCK_b, MCK__41_ }, },
8935 { 0 /* */, Hexagon::V6_vgth_and, Convert__Reg1_0__Tie0_0_0__Reg1_7__Reg1_10, AMFBS_UseHVXV60, { MCK_HvxQR, MCK__38_, MCK__61_, MCK_vcmp, MCK__DOT_, MCK_gt, MCK__40_, MCK_HvxVR, MCK__DOT_, MCK_h, MCK_HvxVR, MCK__DOT_, MCK_h, MCK__41_ }, },
8936 { 0 /* */, Hexagon::V6_vgtub_and, Convert__Reg1_0__Tie0_0_0__Reg1_7__Reg1_10, AMFBS_UseHVXV60, { MCK_HvxQR, MCK__38_, MCK__61_, MCK_vcmp, MCK__DOT_, MCK_gt, MCK__40_, MCK_HvxVR, MCK__DOT_, MCK_ub, MCK_HvxVR, MCK__DOT_, MCK_ub, MCK__41_ }, },
8937 { 0 /* */, Hexagon::V6_vgtuh_and, Convert__Reg1_0__Tie0_0_0__Reg1_7__Reg1_10, AMFBS_UseHVXV60, { MCK_HvxQR, MCK__38_, MCK__61_, MCK_vcmp, MCK__DOT_, MCK_gt, MCK__40_, MCK_HvxVR, MCK__DOT_, MCK_uh, MCK_HvxVR, MCK__DOT_, MCK_uh, MCK__41_ }, },
8938 { 0 /* */, Hexagon::V6_vgtuw_and, Convert__Reg1_0__Tie0_0_0__Reg1_7__Reg1_10, AMFBS_UseHVXV60, { MCK_HvxQR, MCK__38_, MCK__61_, MCK_vcmp, MCK__DOT_, MCK_gt, MCK__40_, MCK_HvxVR, MCK__DOT_, MCK_uw, MCK_HvxVR, MCK__DOT_, MCK_uw, MCK__41_ }, },
8939 { 0 /* */, Hexagon::V6_vgtw_and, Convert__Reg1_0__Tie0_0_0__Reg1_7__Reg1_10, AMFBS_UseHVXV60, { MCK_HvxQR, MCK__38_, MCK__61_, MCK_vcmp, MCK__DOT_, MCK_gt, MCK__40_, MCK_HvxVR, MCK__DOT_, MCK_w, MCK_HvxVR, MCK__DOT_, MCK_w, MCK__41_ }, },
9945 { 205 /* memb */, Hexagon::L4_and_memopb_io, Convert__Reg1_2__imm_95_0__Reg1_6, AMFBS_None, { MCK_memb, MCK__40_, MCK_IntRegs, MCK__41_, MCK__38_, MCK__61_, MCK_IntRegs }, },
9960 { 205 /* memb */, Hexagon::L4_and_memopb_io, Convert__Reg1_2__u32_0Imm1_5__Reg1_9, AMFBS_None, { MCK_memb, MCK__40_, MCK_IntRegs, MCK__43_, MCK__HASH_, MCK_u32_0Imm, MCK__41_, MCK__38_, MCK__61_, MCK_IntRegs }, },
10001 { 234 /* memh */, Hexagon::L4_and_memoph_io, Convert__Reg1_2__imm_95_0__Reg1_6, AMFBS_None, { MCK_memh, MCK__40_, MCK_IntRegs, MCK__41_, MCK__38_, MCK__61_, MCK_IntRegs }, },
10018 { 234 /* memh */, Hexagon::L4_and_memoph_io, Convert__Reg1_2__u31_1Imm1_5__Reg1_9, AMFBS_None, { MCK_memh, MCK__40_, MCK_IntRegs, MCK__43_, MCK__HASH_, MCK_u31_1Imm, MCK__41_, MCK__38_, MCK__61_, MCK_IntRegs }, },
10055 { 239 /* memw */, Hexagon::L4_and_memopw_io, Convert__Reg1_2__imm_95_0__Reg1_6, AMFBS_None, { MCK_memw, MCK__40_, MCK_IntRegs, MCK__41_, MCK__38_, MCK__61_, MCK_IntRegs }, },
10070 { 239 /* memw */, Hexagon::L4_and_memopw_io, Convert__Reg1_2__u30_2Imm1_5__Reg1_9, AMFBS_None, { MCK_memw, MCK__40_, MCK_IntRegs, MCK__43_, MCK__HASH_, MCK_u30_2Imm, MCK__41_, MCK__38_, MCK__61_, MCK_IntRegs }, },