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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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References
gen/lib/Target/Hexagon/HexagonGenAsmMatcher.inc 6263 case MCK_ModRegs:
6702 case Hexagon::M0: OpKind = MCK_ModRegs; break;
6703 case Hexagon::M1: OpKind = MCK_ModRegs; break;
7371 case MCK_ModRegs: return "MCK_ModRegs";
8281 { 0 /* */, Hexagon::L2_loadalignb_pr, Convert__Reg1_0__Reg1_4__Tie0_0_0__Tie1_0_0__Reg1_7, AMFBS_None, { MCK_DoubleRegs, MCK__61_, MCK_memb_95_fifo, MCK__40_, MCK_IntRegs, MCK__43_, MCK__43_, MCK_ModRegs, MCK__41_ }, },
8284 { 0 /* */, Hexagon::L2_loadbsw4_pr, Convert__Reg1_0__Reg1_4__Tie1_0_0__Reg1_7, AMFBS_None, { MCK_DoubleRegs, MCK__61_, MCK_membh, MCK__40_, MCK_IntRegs, MCK__43_, MCK__43_, MCK_ModRegs, MCK__41_ }, },
8288 { 0 /* */, Hexagon::L2_loadrd_pr, Convert__Reg1_0__Reg1_4__Tie1_0_0__Reg1_7, AMFBS_None, { MCK_DoubleRegs, MCK__61_, MCK_memd, MCK__40_, MCK_IntRegs, MCK__43_, MCK__43_, MCK_ModRegs, MCK__41_ }, },
8291 { 0 /* */, Hexagon::L2_loadalignh_pr, Convert__Reg1_0__Reg1_4__Tie0_0_0__Tie1_0_0__Reg1_7, AMFBS_None, { MCK_DoubleRegs, MCK__61_, MCK_memh_95_fifo, MCK__40_, MCK_IntRegs, MCK__43_, MCK__43_, MCK_ModRegs, MCK__41_ }, },
8294 { 0 /* */, Hexagon::L2_loadbzw4_pr, Convert__Reg1_0__Reg1_4__Tie1_0_0__Reg1_7, AMFBS_None, { MCK_DoubleRegs, MCK__61_, MCK_memubh, MCK__40_, MCK_IntRegs, MCK__43_, MCK__43_, MCK_ModRegs, MCK__41_ }, },
8380 { 0 /* */, Hexagon::L2_loadrb_pr, Convert__Reg1_0__Reg1_4__Tie1_0_0__Reg1_7, AMFBS_None, { MCK_IntRegs, MCK__61_, MCK_memb, MCK__40_, MCK_IntRegs, MCK__43_, MCK__43_, MCK_ModRegs, MCK__41_ }, },
8383 { 0 /* */, Hexagon::L2_loadbsw2_pr, Convert__Reg1_0__Reg1_4__Tie1_0_0__Reg1_7, AMFBS_None, { MCK_IntRegs, MCK__61_, MCK_membh, MCK__40_, MCK_IntRegs, MCK__43_, MCK__43_, MCK_ModRegs, MCK__41_ }, },
8387 { 0 /* */, Hexagon::L2_loadrh_pr, Convert__Reg1_0__Reg1_4__Tie1_0_0__Reg1_7, AMFBS_None, { MCK_IntRegs, MCK__61_, MCK_memh, MCK__40_, MCK_IntRegs, MCK__43_, MCK__43_, MCK_ModRegs, MCK__41_ }, },
8391 { 0 /* */, Hexagon::L2_loadrub_pr, Convert__Reg1_0__Reg1_4__Tie1_0_0__Reg1_7, AMFBS_None, { MCK_IntRegs, MCK__61_, MCK_memub, MCK__40_, MCK_IntRegs, MCK__43_, MCK__43_, MCK_ModRegs, MCK__41_ }, },
8394 { 0 /* */, Hexagon::L2_loadbzw2_pr, Convert__Reg1_0__Reg1_4__Tie1_0_0__Reg1_7, AMFBS_None, { MCK_IntRegs, MCK__61_, MCK_memubh, MCK__40_, MCK_IntRegs, MCK__43_, MCK__43_, MCK_ModRegs, MCK__41_ }, },
8398 { 0 /* */, Hexagon::L2_loadruh_pr, Convert__Reg1_0__Reg1_4__Tie1_0_0__Reg1_7, AMFBS_None, { MCK_IntRegs, MCK__61_, MCK_memuh, MCK__40_, MCK_IntRegs, MCK__43_, MCK__43_, MCK_ModRegs, MCK__41_ }, },
8402 { 0 /* */, Hexagon::L2_loadri_pr, Convert__Reg1_0__Reg1_4__Tie1_0_0__Reg1_7, AMFBS_None, { MCK_IntRegs, MCK__61_, MCK_memw, MCK__40_, MCK_IntRegs, MCK__43_, MCK__43_, MCK_ModRegs, MCK__41_ }, },
8447 { 0 /* */, Hexagon::V6_vL32b_ppu, Convert__Reg1_0__Reg1_4__Tie1_0_0__Reg1_7, AMFBS_UseHVXV60, { MCK_HvxVR, MCK__61_, MCK_vmem, MCK__40_, MCK_IntRegs, MCK__43_, MCK__43_, MCK_ModRegs, MCK__41_ }, },
8449 { 0 /* */, Hexagon::V6_vL32Ub_ppu, Convert__Reg1_0__Reg1_4__Tie1_0_0__Reg1_7, AMFBS_UseHVXV60, { MCK_HvxVR, MCK__61_, MCK_vmemu, MCK__40_, MCK_IntRegs, MCK__43_, MCK__43_, MCK_ModRegs, MCK__41_ }, },
8591 { 0 /* */, Hexagon::L2_loadalignb_pbr, Convert__Reg1_0__Reg1_4__Tie0_0_0__Tie1_0_0__Reg1_7, AMFBS_None, { MCK_DoubleRegs, MCK__61_, MCK_memb_95_fifo, MCK__40_, MCK_IntRegs, MCK__43_, MCK__43_, MCK_ModRegs, MCK__COLON_, MCK_brev, MCK__41_ }, },
8592 { 0 /* */, Hexagon::L2_loadbsw4_pbr, Convert__Reg1_0__Reg1_4__Tie1_0_0__Reg1_7, AMFBS_None, { MCK_DoubleRegs, MCK__61_, MCK_membh, MCK__40_, MCK_IntRegs, MCK__43_, MCK__43_, MCK_ModRegs, MCK__COLON_, MCK_brev, MCK__41_ }, },
8593 { 0 /* */, Hexagon::L2_loadrd_pbr, Convert__Reg1_0__Reg1_4__Tie1_0_0__Reg1_7, AMFBS_None, { MCK_DoubleRegs, MCK__61_, MCK_memd, MCK__40_, MCK_IntRegs, MCK__43_, MCK__43_, MCK_ModRegs, MCK__COLON_, MCK_brev, MCK__41_ }, },
8594 { 0 /* */, Hexagon::L2_loadalignh_pbr, Convert__Reg1_0__Reg1_4__Tie0_0_0__Tie1_0_0__Reg1_7, AMFBS_None, { MCK_DoubleRegs, MCK__61_, MCK_memh_95_fifo, MCK__40_, MCK_IntRegs, MCK__43_, MCK__43_, MCK_ModRegs, MCK__COLON_, MCK_brev, MCK__41_ }, },
8595 { 0 /* */, Hexagon::L2_loadbzw4_pbr, Convert__Reg1_0__Reg1_4__Tie1_0_0__Reg1_7, AMFBS_None, { MCK_DoubleRegs, MCK__61_, MCK_memubh, MCK__40_, MCK_IntRegs, MCK__43_, MCK__43_, MCK_ModRegs, MCK__COLON_, MCK_brev, MCK__41_ }, },
8630 { 0 /* */, Hexagon::L2_loadrb_pbr, Convert__Reg1_0__Reg1_4__Tie1_0_0__Reg1_7, AMFBS_None, { MCK_IntRegs, MCK__61_, MCK_memb, MCK__40_, MCK_IntRegs, MCK__43_, MCK__43_, MCK_ModRegs, MCK__COLON_, MCK_brev, MCK__41_ }, },
8631 { 0 /* */, Hexagon::L2_loadbsw2_pbr, Convert__Reg1_0__Reg1_4__Tie1_0_0__Reg1_7, AMFBS_None, { MCK_IntRegs, MCK__61_, MCK_membh, MCK__40_, MCK_IntRegs, MCK__43_, MCK__43_, MCK_ModRegs, MCK__COLON_, MCK_brev, MCK__41_ }, },
8632 { 0 /* */, Hexagon::L2_loadrh_pbr, Convert__Reg1_0__Reg1_4__Tie1_0_0__Reg1_7, AMFBS_None, { MCK_IntRegs, MCK__61_, MCK_memh, MCK__40_, MCK_IntRegs, MCK__43_, MCK__43_, MCK_ModRegs, MCK__COLON_, MCK_brev, MCK__41_ }, },
8633 { 0 /* */, Hexagon::L2_loadrub_pbr, Convert__Reg1_0__Reg1_4__Tie1_0_0__Reg1_7, AMFBS_None, { MCK_IntRegs, MCK__61_, MCK_memub, MCK__40_, MCK_IntRegs, MCK__43_, MCK__43_, MCK_ModRegs, MCK__COLON_, MCK_brev, MCK__41_ }, },
8634 { 0 /* */, Hexagon::L2_loadbzw2_pbr, Convert__Reg1_0__Reg1_4__Tie1_0_0__Reg1_7, AMFBS_None, { MCK_IntRegs, MCK__61_, MCK_memubh, MCK__40_, MCK_IntRegs, MCK__43_, MCK__43_, MCK_ModRegs, MCK__COLON_, MCK_brev, MCK__41_ }, },
8635 { 0 /* */, Hexagon::L2_loadruh_pbr, Convert__Reg1_0__Reg1_4__Tie1_0_0__Reg1_7, AMFBS_None, { MCK_IntRegs, MCK__61_, MCK_memuh, MCK__40_, MCK_IntRegs, MCK__43_, MCK__43_, MCK_ModRegs, MCK__COLON_, MCK_brev, MCK__41_ }, },
8636 { 0 /* */, Hexagon::L2_loadri_pbr, Convert__Reg1_0__Reg1_4__Tie1_0_0__Reg1_7, AMFBS_None, { MCK_IntRegs, MCK__61_, MCK_memw, MCK__40_, MCK_IntRegs, MCK__43_, MCK__43_, MCK_ModRegs, MCK__COLON_, MCK_brev, MCK__41_ }, },
8652 { 0 /* */, Hexagon::V6_vL32b_cur_ppu, Convert__Reg1_0__Reg1_6__Tie1_0_0__Reg1_9, AMFBS_UseHVXV60, { MCK_HvxVR, MCK__DOT_, MCK_cur, MCK__61_, MCK_vmem, MCK__40_, MCK_IntRegs, MCK__43_, MCK__43_, MCK_ModRegs, MCK__41_ }, },
8656 { 0 /* */, Hexagon::V6_vL32b_tmp_ppu, Convert__Reg1_0__Reg1_6__Tie1_0_0__Reg1_9, AMFBS_UseHVXV60, { MCK_HvxVR, MCK__DOT_, MCK_tmp, MCK__61_, MCK_vmem, MCK__40_, MCK_IntRegs, MCK__43_, MCK__43_, MCK_ModRegs, MCK__41_ }, },
8664 { 0 /* */, Hexagon::V6_vL32b_nt_ppu, Convert__Reg1_0__Reg1_4__Tie1_0_0__Reg1_7, AMFBS_UseHVXV60, { MCK_HvxVR, MCK__61_, MCK_vmem, MCK__40_, MCK_IntRegs, MCK__43_, MCK__43_, MCK_ModRegs, MCK__41_, MCK__COLON_, MCK_nt }, },
8866 { 0 /* */, Hexagon::V6_vL32b_nt_cur_ppu, Convert__Reg1_0__Reg1_6__Tie1_0_0__Reg1_9, AMFBS_UseHVXV60, { MCK_HvxVR, MCK__DOT_, MCK_cur, MCK__61_, MCK_vmem, MCK__40_, MCK_IntRegs, MCK__43_, MCK__43_, MCK_ModRegs, MCK__41_, MCK__COLON_, MCK_nt }, },
8886 { 0 /* */, Hexagon::V6_vL32b_nt_tmp_ppu, Convert__Reg1_0__Reg1_6__Tie1_0_0__Reg1_9, AMFBS_UseHVXV60, { MCK_HvxVR, MCK__DOT_, MCK_tmp, MCK__61_, MCK_vmem, MCK__40_, MCK_IntRegs, MCK__43_, MCK__43_, MCK_ModRegs, MCK__41_, MCK__COLON_, MCK_nt }, },
8982 { 0 /* */, Hexagon::L2_loadalignb_pcr, Convert__Reg1_0__Reg1_4__Tie0_0_0__Tie1_0_0__Reg1_11, AMFBS_None, { MCK_DoubleRegs, MCK__61_, MCK_memb_95_fifo, MCK__40_, MCK_IntRegs, MCK__43_, MCK__43_, MCK_I, MCK__COLON_, MCK_circ, MCK__40_, MCK_ModRegs, MCK__41_, MCK__41_ }, },
8983 { 0 /* */, Hexagon::L2_loadbsw4_pcr, Convert__Reg1_0__Reg1_4__Tie1_0_0__Reg1_11, AMFBS_None, { MCK_DoubleRegs, MCK__61_, MCK_membh, MCK__40_, MCK_IntRegs, MCK__43_, MCK__43_, MCK_I, MCK__COLON_, MCK_circ, MCK__40_, MCK_ModRegs, MCK__41_, MCK__41_ }, },
8984 { 0 /* */, Hexagon::L2_loadrd_pcr, Convert__Reg1_0__Reg1_4__Tie1_0_0__Reg1_11, AMFBS_None, { MCK_DoubleRegs, MCK__61_, MCK_memd, MCK__40_, MCK_IntRegs, MCK__43_, MCK__43_, MCK_I, MCK__COLON_, MCK_circ, MCK__40_, MCK_ModRegs, MCK__41_, MCK__41_ }, },
8985 { 0 /* */, Hexagon::L2_loadalignh_pcr, Convert__Reg1_0__Reg1_4__Tie0_0_0__Tie1_0_0__Reg1_11, AMFBS_None, { MCK_DoubleRegs, MCK__61_, MCK_memh_95_fifo, MCK__40_, MCK_IntRegs, MCK__43_, MCK__43_, MCK_I, MCK__COLON_, MCK_circ, MCK__40_, MCK_ModRegs, MCK__41_, MCK__41_ }, },
8986 { 0 /* */, Hexagon::L2_loadbzw4_pcr, Convert__Reg1_0__Reg1_4__Tie1_0_0__Reg1_11, AMFBS_None, { MCK_DoubleRegs, MCK__61_, MCK_memubh, MCK__40_, MCK_IntRegs, MCK__43_, MCK__43_, MCK_I, MCK__COLON_, MCK_circ, MCK__40_, MCK_ModRegs, MCK__41_, MCK__41_ }, },
9025 { 0 /* */, Hexagon::L2_loadrb_pcr, Convert__Reg1_0__Reg1_4__Tie1_0_0__Reg1_11, AMFBS_None, { MCK_IntRegs, MCK__61_, MCK_memb, MCK__40_, MCK_IntRegs, MCK__43_, MCK__43_, MCK_I, MCK__COLON_, MCK_circ, MCK__40_, MCK_ModRegs, MCK__41_, MCK__41_ }, },
9026 { 0 /* */, Hexagon::L2_loadbsw2_pcr, Convert__Reg1_0__Reg1_4__Tie1_0_0__Reg1_11, AMFBS_None, { MCK_IntRegs, MCK__61_, MCK_membh, MCK__40_, MCK_IntRegs, MCK__43_, MCK__43_, MCK_I, MCK__COLON_, MCK_circ, MCK__40_, MCK_ModRegs, MCK__41_, MCK__41_ }, },
9027 { 0 /* */, Hexagon::L2_loadrh_pcr, Convert__Reg1_0__Reg1_4__Tie1_0_0__Reg1_11, AMFBS_None, { MCK_IntRegs, MCK__61_, MCK_memh, MCK__40_, MCK_IntRegs, MCK__43_, MCK__43_, MCK_I, MCK__COLON_, MCK_circ, MCK__40_, MCK_ModRegs, MCK__41_, MCK__41_ }, },
9028 { 0 /* */, Hexagon::L2_loadrub_pcr, Convert__Reg1_0__Reg1_4__Tie1_0_0__Reg1_11, AMFBS_None, { MCK_IntRegs, MCK__61_, MCK_memub, MCK__40_, MCK_IntRegs, MCK__43_, MCK__43_, MCK_I, MCK__COLON_, MCK_circ, MCK__40_, MCK_ModRegs, MCK__41_, MCK__41_ }, },
9029 { 0 /* */, Hexagon::L2_loadbzw2_pcr, Convert__Reg1_0__Reg1_4__Tie1_0_0__Reg1_11, AMFBS_None, { MCK_IntRegs, MCK__61_, MCK_memubh, MCK__40_, MCK_IntRegs, MCK__43_, MCK__43_, MCK_I, MCK__COLON_, MCK_circ, MCK__40_, MCK_ModRegs, MCK__41_, MCK__41_ }, },
9030 { 0 /* */, Hexagon::L2_loadruh_pcr, Convert__Reg1_0__Reg1_4__Tie1_0_0__Reg1_11, AMFBS_None, { MCK_IntRegs, MCK__61_, MCK_memuh, MCK__40_, MCK_IntRegs, MCK__43_, MCK__43_, MCK_I, MCK__COLON_, MCK_circ, MCK__40_, MCK_ModRegs, MCK__41_, MCK__41_ }, },
9031 { 0 /* */, Hexagon::L2_loadri_pcr, Convert__Reg1_0__Reg1_4__Tie1_0_0__Reg1_11, AMFBS_None, { MCK_IntRegs, MCK__61_, MCK_memw, MCK__40_, MCK_IntRegs, MCK__43_, MCK__43_, MCK_I, MCK__COLON_, MCK_circ, MCK__40_, MCK_ModRegs, MCK__41_, MCK__41_ }, },
9060 { 0 /* */, Hexagon::L2_loadalignb_pci, Convert__Reg1_0__Reg1_4__Tie0_0_0__Tie1_0_0__s4_0Imm1_8__Reg1_12, AMFBS_None, { MCK_DoubleRegs, MCK__61_, MCK_memb_95_fifo, MCK__40_, MCK_IntRegs, MCK__43_, MCK__43_, MCK__HASH_, MCK_s4_0Imm, MCK__COLON_, MCK_circ, MCK__40_, MCK_ModRegs, MCK__41_, MCK__41_ }, },
9061 { 0 /* */, Hexagon::L2_loadbsw4_pci, Convert__Reg1_0__Reg1_4__Tie1_0_0__s4_2Imm1_8__Reg1_12, AMFBS_None, { MCK_DoubleRegs, MCK__61_, MCK_membh, MCK__40_, MCK_IntRegs, MCK__43_, MCK__43_, MCK__HASH_, MCK_s4_2Imm, MCK__COLON_, MCK_circ, MCK__40_, MCK_ModRegs, MCK__41_, MCK__41_ }, },
9062 { 0 /* */, Hexagon::L2_loadrd_pci, Convert__Reg1_0__Reg1_4__Tie1_0_0__s4_3Imm1_8__Reg1_12, AMFBS_None, { MCK_DoubleRegs, MCK__61_, MCK_memd, MCK__40_, MCK_IntRegs, MCK__43_, MCK__43_, MCK__HASH_, MCK_s4_3Imm, MCK__COLON_, MCK_circ, MCK__40_, MCK_ModRegs, MCK__41_, MCK__41_ }, },
9063 { 0 /* */, Hexagon::L2_loadalignh_pci, Convert__Reg1_0__Reg1_4__Tie0_0_0__Tie1_0_0__s4_1Imm1_8__Reg1_12, AMFBS_None, { MCK_DoubleRegs, MCK__61_, MCK_memh_95_fifo, MCK__40_, MCK_IntRegs, MCK__43_, MCK__43_, MCK__HASH_, MCK_s4_1Imm, MCK__COLON_, MCK_circ, MCK__40_, MCK_ModRegs, MCK__41_, MCK__41_ }, },
9064 { 0 /* */, Hexagon::L2_loadbzw4_pci, Convert__Reg1_0__Reg1_4__Tie1_0_0__s4_2Imm1_8__Reg1_12, AMFBS_None, { MCK_DoubleRegs, MCK__61_, MCK_memubh, MCK__40_, MCK_IntRegs, MCK__43_, MCK__43_, MCK__HASH_, MCK_s4_2Imm, MCK__COLON_, MCK_circ, MCK__40_, MCK_ModRegs, MCK__41_, MCK__41_ }, },
9103 { 0 /* */, Hexagon::L2_loadrb_pci, Convert__Reg1_0__Reg1_4__Tie1_0_0__s4_0Imm1_8__Reg1_12, AMFBS_None, { MCK_IntRegs, MCK__61_, MCK_memb, MCK__40_, MCK_IntRegs, MCK__43_, MCK__43_, MCK__HASH_, MCK_s4_0Imm, MCK__COLON_, MCK_circ, MCK__40_, MCK_ModRegs, MCK__41_, MCK__41_ }, },
9104 { 0 /* */, Hexagon::L2_loadbsw2_pci, Convert__Reg1_0__Reg1_4__Tie1_0_0__s4_1Imm1_8__Reg1_12, AMFBS_None, { MCK_IntRegs, MCK__61_, MCK_membh, MCK__40_, MCK_IntRegs, MCK__43_, MCK__43_, MCK__HASH_, MCK_s4_1Imm, MCK__COLON_, MCK_circ, MCK__40_, MCK_ModRegs, MCK__41_, MCK__41_ }, },
9105 { 0 /* */, Hexagon::L2_loadrh_pci, Convert__Reg1_0__Reg1_4__Tie1_0_0__s4_1Imm1_8__Reg1_12, AMFBS_None, { MCK_IntRegs, MCK__61_, MCK_memh, MCK__40_, MCK_IntRegs, MCK__43_, MCK__43_, MCK__HASH_, MCK_s4_1Imm, MCK__COLON_, MCK_circ, MCK__40_, MCK_ModRegs, MCK__41_, MCK__41_ }, },
9106 { 0 /* */, Hexagon::L2_loadrub_pci, Convert__Reg1_0__Reg1_4__Tie1_0_0__s4_0Imm1_8__Reg1_12, AMFBS_None, { MCK_IntRegs, MCK__61_, MCK_memub, MCK__40_, MCK_IntRegs, MCK__43_, MCK__43_, MCK__HASH_, MCK_s4_0Imm, MCK__COLON_, MCK_circ, MCK__40_, MCK_ModRegs, MCK__41_, MCK__41_ }, },
9107 { 0 /* */, Hexagon::L2_loadbzw2_pci, Convert__Reg1_0__Reg1_4__Tie1_0_0__s4_1Imm1_8__Reg1_12, AMFBS_None, { MCK_IntRegs, MCK__61_, MCK_memubh, MCK__40_, MCK_IntRegs, MCK__43_, MCK__43_, MCK__HASH_, MCK_s4_1Imm, MCK__COLON_, MCK_circ, MCK__40_, MCK_ModRegs, MCK__41_, MCK__41_ }, },
9108 { 0 /* */, Hexagon::L2_loadruh_pci, Convert__Reg1_0__Reg1_4__Tie1_0_0__s4_1Imm1_8__Reg1_12, AMFBS_None, { MCK_IntRegs, MCK__61_, MCK_memuh, MCK__40_, MCK_IntRegs, MCK__43_, MCK__43_, MCK__HASH_, MCK_s4_1Imm, MCK__COLON_, MCK_circ, MCK__40_, MCK_ModRegs, MCK__41_, MCK__41_ }, },
9109 { 0 /* */, Hexagon::L2_loadri_pci, Convert__Reg1_0__Reg1_4__Tie1_0_0__s4_2Imm1_8__Reg1_12, AMFBS_None, { MCK_IntRegs, MCK__61_, MCK_memw, MCK__40_, MCK_IntRegs, MCK__43_, MCK__43_, MCK__HASH_, MCK_s4_2Imm, MCK__COLON_, MCK_circ, MCK__40_, MCK_ModRegs, MCK__41_, MCK__41_ }, },
9532 { 158 /* if */, Hexagon::V6_vS32b_qpred_ppu, Convert__Reg1_6__Reg1_2__Tie0_0_0__Reg1_9__Reg1_12, AMFBS_UseHVXV60, { MCK_if, MCK__40_, MCK_HvxQR, MCK__41_, MCK_vmem, MCK__40_, MCK_IntRegs, MCK__43_, MCK__43_, MCK_ModRegs, MCK__41_, MCK__61_, MCK_HvxVR }, },
9542 { 158 /* if */, Hexagon::V6_vS32b_pred_ppu, Convert__Reg1_6__Reg1_2__Tie0_0_0__Reg1_9__Reg1_12, AMFBS_UseHVXV60, { MCK_if, MCK__40_, MCK_PredRegs, MCK__41_, MCK_vmem, MCK__40_, MCK_IntRegs, MCK__43_, MCK__43_, MCK_ModRegs, MCK__41_, MCK__61_, MCK_HvxVR }, },
9544 { 158 /* if */, Hexagon::V6_vS32Ub_pred_ppu, Convert__Reg1_6__Reg1_2__Tie0_0_0__Reg1_9__Reg1_12, AMFBS_UseHVXV60, { MCK_if, MCK__40_, MCK_PredRegs, MCK__41_, MCK_vmemu, MCK__40_, MCK_IntRegs, MCK__43_, MCK__43_, MCK_ModRegs, MCK__41_, MCK__61_, MCK_HvxVR }, },
9546 { 158 /* if */, Hexagon::V6_zLd_pred_ppu, Convert__Reg1_8__Reg1_2__Tie0_0_0__Reg1_11, AMFBS_UseHVXV66_UseZReg, { MCK_if, MCK__40_, MCK_PredRegs, MCK__41_, MCK_z, MCK__61_, MCK_vmem, MCK__40_, MCK_IntRegs, MCK__43_, MCK__43_, MCK_ModRegs, MCK__41_ }, },
9554 { 158 /* if */, Hexagon::V6_vL32b_pred_ppu, Convert__Reg1_4__Reg1_8__Reg1_2__Tie1_0_0__Reg1_11, AMFBS_UseHVXV62, { MCK_if, MCK__40_, MCK_PredRegs, MCK__41_, MCK_HvxVR, MCK__61_, MCK_vmem, MCK__40_, MCK_IntRegs, MCK__43_, MCK__43_, MCK_ModRegs, MCK__41_ }, },
9575 { 158 /* if */, Hexagon::V6_vS32b_nqpred_ppu, Convert__Reg1_7__Reg1_3__Tie0_0_0__Reg1_10__Reg1_13, AMFBS_UseHVXV60, { MCK_if, MCK__40_, MCK__EXCLAIM_, MCK_HvxQR, MCK__41_, MCK_vmem, MCK__40_, MCK_IntRegs, MCK__43_, MCK__43_, MCK_ModRegs, MCK__41_, MCK__61_, MCK_HvxVR }, },
9585 { 158 /* if */, Hexagon::V6_vS32b_npred_ppu, Convert__Reg1_7__Reg1_3__Tie0_0_0__Reg1_10__Reg1_13, AMFBS_UseHVXV60, { MCK_if, MCK__40_, MCK__EXCLAIM_, MCK_PredRegs, MCK__41_, MCK_vmem, MCK__40_, MCK_IntRegs, MCK__43_, MCK__43_, MCK_ModRegs, MCK__41_, MCK__61_, MCK_HvxVR }, },
9587 { 158 /* if */, Hexagon::V6_vS32Ub_npred_ppu, Convert__Reg1_7__Reg1_3__Tie0_0_0__Reg1_10__Reg1_13, AMFBS_UseHVXV60, { MCK_if, MCK__40_, MCK__EXCLAIM_, MCK_PredRegs, MCK__41_, MCK_vmemu, MCK__40_, MCK_IntRegs, MCK__43_, MCK__43_, MCK_ModRegs, MCK__41_, MCK__61_, MCK_HvxVR }, },
9595 { 158 /* if */, Hexagon::V6_vL32b_npred_ppu, Convert__Reg1_5__Reg1_9__Reg1_3__Tie1_0_0__Reg1_12, AMFBS_UseHVXV62, { MCK_if, MCK__40_, MCK__EXCLAIM_, MCK_PredRegs, MCK__41_, MCK_HvxVR, MCK__61_, MCK_vmem, MCK__40_, MCK_IntRegs, MCK__43_, MCK__43_, MCK_ModRegs, MCK__41_ }, },
9679 { 158 /* if */, Hexagon::V6_vS32b_nt_qpred_ppu, Convert__Reg1_6__Reg1_2__Tie0_0_0__Reg1_9__Reg1_14, AMFBS_UseHVXV60, { MCK_if, MCK__40_, MCK_HvxQR, MCK__41_, MCK_vmem, MCK__40_, MCK_IntRegs, MCK__43_, MCK__43_, MCK_ModRegs, MCK__41_, MCK__COLON_, MCK_nt, MCK__61_, MCK_HvxVR }, },
9686 { 158 /* if */, Hexagon::V6_vS32b_nt_pred_ppu, Convert__Reg1_6__Reg1_2__Tie0_0_0__Reg1_9__Reg1_14, AMFBS_UseHVXV60, { MCK_if, MCK__40_, MCK_PredRegs, MCK__41_, MCK_vmem, MCK__40_, MCK_IntRegs, MCK__43_, MCK__43_, MCK_ModRegs, MCK__41_, MCK__COLON_, MCK_nt, MCK__61_, MCK_HvxVR }, },
9687 { 158 /* if */, Hexagon::V6_vS32b_new_pred_ppu, Convert__Reg1_6__Reg1_2__Tie0_0_0__Reg1_9__Reg1_12, AMFBS_UseHVXV60, { MCK_if, MCK__40_, MCK_PredRegs, MCK__41_, MCK_vmem, MCK__40_, MCK_IntRegs, MCK__43_, MCK__43_, MCK_ModRegs, MCK__41_, MCK__61_, MCK_HvxVR, MCK__DOT_, MCK_new }, },
9689 { 158 /* if */, Hexagon::V6_vL32b_cur_pred_ppu, Convert__Reg1_4__Reg1_10__Reg1_2__Tie1_0_0__Reg1_13, AMFBS_UseHVXV62, { MCK_if, MCK__40_, MCK_PredRegs, MCK__41_, MCK_HvxVR, MCK__DOT_, MCK_cur, MCK__61_, MCK_vmem, MCK__40_, MCK_IntRegs, MCK__43_, MCK__43_, MCK_ModRegs, MCK__41_ }, },
9691 { 158 /* if */, Hexagon::V6_vL32b_tmp_pred_ppu, Convert__Reg1_4__Reg1_10__Reg1_2__Tie1_0_0__Reg1_13, AMFBS_UseHVXV62, { MCK_if, MCK__40_, MCK_PredRegs, MCK__41_, MCK_HvxVR, MCK__DOT_, MCK_tmp, MCK__61_, MCK_vmem, MCK__40_, MCK_IntRegs, MCK__43_, MCK__43_, MCK_ModRegs, MCK__41_ }, },
9693 { 158 /* if */, Hexagon::V6_vL32b_nt_pred_ppu, Convert__Reg1_4__Reg1_8__Reg1_2__Tie1_0_0__Reg1_11, AMFBS_UseHVXV62, { MCK_if, MCK__40_, MCK_PredRegs, MCK__41_, MCK_HvxVR, MCK__61_, MCK_vmem, MCK__40_, MCK_IntRegs, MCK__43_, MCK__43_, MCK_ModRegs, MCK__41_, MCK__COLON_, MCK_nt }, },
9711 { 158 /* if */, Hexagon::V6_vS32b_nt_nqpred_ppu, Convert__Reg1_7__Reg1_3__Tie0_0_0__Reg1_10__Reg1_15, AMFBS_UseHVXV60, { MCK_if, MCK__40_, MCK__EXCLAIM_, MCK_HvxQR, MCK__41_, MCK_vmem, MCK__40_, MCK_IntRegs, MCK__43_, MCK__43_, MCK_ModRegs, MCK__41_, MCK__COLON_, MCK_nt, MCK__61_, MCK_HvxVR }, },
9718 { 158 /* if */, Hexagon::V6_vS32b_nt_npred_ppu, Convert__Reg1_7__Reg1_3__Tie0_0_0__Reg1_10__Reg1_15, AMFBS_UseHVXV60, { MCK_if, MCK__40_, MCK__EXCLAIM_, MCK_PredRegs, MCK__41_, MCK_vmem, MCK__40_, MCK_IntRegs, MCK__43_, MCK__43_, MCK_ModRegs, MCK__41_, MCK__COLON_, MCK_nt, MCK__61_, MCK_HvxVR }, },
9719 { 158 /* if */, Hexagon::V6_vS32b_new_npred_ppu, Convert__Reg1_7__Reg1_3__Tie0_0_0__Reg1_10__Reg1_13, AMFBS_UseHVXV60, { MCK_if, MCK__40_, MCK__EXCLAIM_, MCK_PredRegs, MCK__41_, MCK_vmem, MCK__40_, MCK_IntRegs, MCK__43_, MCK__43_, MCK_ModRegs, MCK__41_, MCK__61_, MCK_HvxVR, MCK__DOT_, MCK_new }, },
9721 { 158 /* if */, Hexagon::V6_vL32b_cur_npred_ppu, Convert__Reg1_5__Reg1_11__Reg1_3__Tie1_0_0__Reg1_14, AMFBS_UseHVXV62, { MCK_if, MCK__40_, MCK__EXCLAIM_, MCK_PredRegs, MCK__41_, MCK_HvxVR, MCK__DOT_, MCK_cur, MCK__61_, MCK_vmem, MCK__40_, MCK_IntRegs, MCK__43_, MCK__43_, MCK_ModRegs, MCK__41_ }, },
9723 { 158 /* if */, Hexagon::V6_vL32b_tmp_npred_ppu, Convert__Reg1_5__Reg1_11__Reg1_3__Tie1_0_0__Reg1_14, AMFBS_UseHVXV62, { MCK_if, MCK__40_, MCK__EXCLAIM_, MCK_PredRegs, MCK__41_, MCK_HvxVR, MCK__DOT_, MCK_tmp, MCK__61_, MCK_vmem, MCK__40_, MCK_IntRegs, MCK__43_, MCK__43_, MCK_ModRegs, MCK__41_ }, },
9725 { 158 /* if */, Hexagon::V6_vL32b_nt_npred_ppu, Convert__Reg1_5__Reg1_9__Reg1_3__Tie1_0_0__Reg1_12, AMFBS_UseHVXV62, { MCK_if, MCK__40_, MCK__EXCLAIM_, MCK_PredRegs, MCK__41_, MCK_HvxVR, MCK__61_, MCK_vmem, MCK__40_, MCK_IntRegs, MCK__43_, MCK__43_, MCK_ModRegs, MCK__41_, MCK__COLON_, MCK_nt }, },
9751 { 158 /* if */, Hexagon::V6_vscattermhwq, Convert__Reg1_2__Reg1_6__Reg1_7__Reg1_8__Reg1_15, AMFBS_UseHVXV65, { MCK_if, MCK__40_, MCK_HvxQR, MCK__41_, MCK_vscatter, MCK__40_, MCK_IntRegs, MCK_ModRegs, MCK_HvxWR, MCK__DOT_, MCK_w, MCK__41_, MCK__DOT_, MCK_h, MCK__61_, MCK_HvxVR }, },
9752 { 158 /* if */, Hexagon::V6_vscattermhwq, Convert__Reg1_2__Reg1_6__Reg1_7__Reg1_8__Reg1_13, AMFBS_UseHVX, { MCK_if, MCK__40_, MCK_HvxQR, MCK__41_, MCK_vscatter, MCK__40_, MCK_IntRegs, MCK_ModRegs, MCK_HvxWR, MCK__DOT_, MCK_w, MCK__41_, MCK__61_, MCK_HvxVR, MCK__DOT_, MCK_h }, },
9753 { 158 /* if */, Hexagon::V6_vscattermhq, Convert__Reg1_2__Reg1_6__Reg1_7__Reg1_8__Reg1_15, AMFBS_UseHVXV65, { MCK_if, MCK__40_, MCK_HvxQR, MCK__41_, MCK_vscatter, MCK__40_, MCK_IntRegs, MCK_ModRegs, MCK_HvxVR, MCK__DOT_, MCK_h, MCK__41_, MCK__DOT_, MCK_h, MCK__61_, MCK_HvxVR }, },
9754 { 158 /* if */, Hexagon::V6_vscattermhq, Convert__Reg1_2__Reg1_6__Reg1_7__Reg1_8__Reg1_13, AMFBS_UseHVX, { MCK_if, MCK__40_, MCK_HvxQR, MCK__41_, MCK_vscatter, MCK__40_, MCK_IntRegs, MCK_ModRegs, MCK_HvxVR, MCK__DOT_, MCK_h, MCK__41_, MCK__61_, MCK_HvxVR, MCK__DOT_, MCK_h }, },
9755 { 158 /* if */, Hexagon::V6_vscattermwq, Convert__Reg1_2__Reg1_6__Reg1_7__Reg1_8__Reg1_15, AMFBS_UseHVXV65, { MCK_if, MCK__40_, MCK_HvxQR, MCK__41_, MCK_vscatter, MCK__40_, MCK_IntRegs, MCK_ModRegs, MCK_HvxVR, MCK__DOT_, MCK_w, MCK__41_, MCK__DOT_, MCK_w, MCK__61_, MCK_HvxVR }, },
9756 { 158 /* if */, Hexagon::V6_vscattermwq, Convert__Reg1_2__Reg1_6__Reg1_7__Reg1_8__Reg1_13, AMFBS_UseHVX, { MCK_if, MCK__40_, MCK_HvxQR, MCK__41_, MCK_vscatter, MCK__40_, MCK_IntRegs, MCK_ModRegs, MCK_HvxVR, MCK__DOT_, MCK_w, MCK__41_, MCK__61_, MCK_HvxVR, MCK__DOT_, MCK_w }, },
9847 { 158 /* if */, Hexagon::V6_vS32b_nt_new_pred_ppu, Convert__Reg1_6__Reg1_2__Tie0_0_0__Reg1_9__Reg1_14, AMFBS_UseHVXV60, { MCK_if, MCK__40_, MCK_PredRegs, MCK__41_, MCK_vmem, MCK__40_, MCK_IntRegs, MCK__43_, MCK__43_, MCK_ModRegs, MCK__41_, MCK__COLON_, MCK_nt, MCK__61_, MCK_HvxVR, MCK__DOT_, MCK_new }, },
9849 { 158 /* if */, Hexagon::V6_vL32b_nt_cur_pred_ppu, Convert__Reg1_4__Reg1_10__Reg1_2__Tie1_0_0__Reg1_13, AMFBS_UseHVXV62, { MCK_if, MCK__40_, MCK_PredRegs, MCK__41_, MCK_HvxVR, MCK__DOT_, MCK_cur, MCK__61_, MCK_vmem, MCK__40_, MCK_IntRegs, MCK__43_, MCK__43_, MCK_ModRegs, MCK__41_, MCK__COLON_, MCK_nt }, },
9851 { 158 /* if */, Hexagon::V6_vL32b_nt_tmp_pred_ppu, Convert__Reg1_4__Reg1_10__Reg1_2__Tie1_0_0__Reg1_13, AMFBS_UseHVXV62, { MCK_if, MCK__40_, MCK_PredRegs, MCK__41_, MCK_HvxVR, MCK__DOT_, MCK_tmp, MCK__61_, MCK_vmem, MCK__40_, MCK_IntRegs, MCK__43_, MCK__43_, MCK_ModRegs, MCK__41_, MCK__COLON_, MCK_nt }, },
9867 { 158 /* if */, Hexagon::V6_vS32b_nt_new_npred_ppu, Convert__Reg1_7__Reg1_3__Tie0_0_0__Reg1_10__Reg1_15, AMFBS_UseHVXV60, { MCK_if, MCK__40_, MCK__EXCLAIM_, MCK_PredRegs, MCK__41_, MCK_vmem, MCK__40_, MCK_IntRegs, MCK__43_, MCK__43_, MCK_ModRegs, MCK__41_, MCK__COLON_, MCK_nt, MCK__61_, MCK_HvxVR, MCK__DOT_, MCK_new }, },
9869 { 158 /* if */, Hexagon::V6_vL32b_nt_cur_npred_ppu, Convert__Reg1_5__Reg1_11__Reg1_3__Tie1_0_0__Reg1_14, AMFBS_UseHVXV62, { MCK_if, MCK__40_, MCK__EXCLAIM_, MCK_PredRegs, MCK__41_, MCK_HvxVR, MCK__DOT_, MCK_cur, MCK__61_, MCK_vmem, MCK__40_, MCK_IntRegs, MCK__43_, MCK__43_, MCK_ModRegs, MCK__41_, MCK__COLON_, MCK_nt }, },
9871 { 158 /* if */, Hexagon::V6_vL32b_nt_tmp_npred_ppu, Convert__Reg1_5__Reg1_11__Reg1_3__Tie1_0_0__Reg1_14, AMFBS_UseHVXV62, { MCK_if, MCK__40_, MCK__EXCLAIM_, MCK_PredRegs, MCK__41_, MCK_HvxVR, MCK__DOT_, MCK_tmp, MCK__61_, MCK_vmem, MCK__40_, MCK_IntRegs, MCK__43_, MCK__43_, MCK_ModRegs, MCK__41_, MCK__COLON_, MCK_nt }, },
9876 { 158 /* if */, Hexagon::V6_vgathermhwq, Convert__Reg1_2__Reg1_10__Reg1_11__Reg1_12, AMFBS_UseHVXV65, { MCK_if, MCK__40_, MCK_HvxQR, MCK__41_, MCK_V65Regs, MCK__DOT_, MCK_h, MCK__61_, MCK_vgather, MCK__40_, MCK_IntRegs, MCK_ModRegs, MCK_HvxWR, MCK__DOT_, MCK_w, MCK__41_, MCK__DOT_, MCK_h }, },
9877 { 158 /* if */, Hexagon::V6_vgathermhq, Convert__Reg1_2__Reg1_10__Reg1_11__Reg1_12, AMFBS_UseHVXV65, { MCK_if, MCK__40_, MCK_HvxQR, MCK__41_, MCK_V65Regs, MCK__DOT_, MCK_h, MCK__61_, MCK_vgather, MCK__40_, MCK_IntRegs, MCK_ModRegs, MCK_HvxVR, MCK__DOT_, MCK_h, MCK__41_, MCK__DOT_, MCK_h }, },
9878 { 158 /* if */, Hexagon::V6_vgathermwq, Convert__Reg1_2__Reg1_10__Reg1_11__Reg1_12, AMFBS_UseHVXV65, { MCK_if, MCK__40_, MCK_HvxQR, MCK__41_, MCK_V65Regs, MCK__DOT_, MCK_w, MCK__61_, MCK_vgather, MCK__40_, MCK_IntRegs, MCK_ModRegs, MCK_HvxVR, MCK__DOT_, MCK_w, MCK__41_, MCK__DOT_, MCK_w }, },
9956 { 205 /* memb */, Hexagon::S2_storerb_pr, Convert__Reg1_2__Tie0_0_0__Reg1_5__Reg1_8, AMFBS_None, { MCK_memb, MCK__40_, MCK_IntRegs, MCK__43_, MCK__43_, MCK_ModRegs, MCK__41_, MCK__61_, MCK_IntRegs }, },
9970 { 205 /* memb */, Hexagon::S2_storerbnew_pr, Convert__Reg1_2__Tie0_0_0__Reg1_5__Reg1_8, AMFBS_None, { MCK_memb, MCK__40_, MCK_IntRegs, MCK__43_, MCK__43_, MCK_ModRegs, MCK__41_, MCK__61_, MCK_IntRegs, MCK__DOT_, MCK_new }, },
9971 { 205 /* memb */, Hexagon::S2_storerb_pbr, Convert__Reg1_2__Tie0_0_0__Reg1_5__Reg1_10, AMFBS_None, { MCK_memb, MCK__40_, MCK_IntRegs, MCK__43_, MCK__43_, MCK_ModRegs, MCK__COLON_, MCK_brev, MCK__41_, MCK__61_, MCK_IntRegs }, },
9977 { 205 /* memb */, Hexagon::S2_storerbnew_pbr, Convert__Reg1_2__Tie0_0_0__Reg1_5__Reg1_10, AMFBS_None, { MCK_memb, MCK__40_, MCK_IntRegs, MCK__43_, MCK__43_, MCK_ModRegs, MCK__COLON_, MCK_brev, MCK__41_, MCK__61_, MCK_IntRegs, MCK__DOT_, MCK_new }, },
9979 { 205 /* memb */, Hexagon::S2_storerb_pcr, Convert__Reg1_2__Tie0_0_0__Reg1_9__Reg1_13, AMFBS_None, { MCK_memb, MCK__40_, MCK_IntRegs, MCK__43_, MCK__43_, MCK_I, MCK__COLON_, MCK_circ, MCK__40_, MCK_ModRegs, MCK__41_, MCK__41_, MCK__61_, MCK_IntRegs }, },
9981 { 205 /* memb */, Hexagon::S2_storerb_pci, Convert__Reg1_2__Tie0_0_0__s4_0Imm1_6__Reg1_10__Reg1_14, AMFBS_None, { MCK_memb, MCK__40_, MCK_IntRegs, MCK__43_, MCK__43_, MCK__HASH_, MCK_s4_0Imm, MCK__COLON_, MCK_circ, MCK__40_, MCK_ModRegs, MCK__41_, MCK__41_, MCK__61_, MCK_IntRegs }, },
9983 { 205 /* memb */, Hexagon::S2_storerbnew_pcr, Convert__Reg1_2__Tie0_0_0__Reg1_9__Reg1_13, AMFBS_None, { MCK_memb, MCK__40_, MCK_IntRegs, MCK__43_, MCK__43_, MCK_I, MCK__COLON_, MCK_circ, MCK__40_, MCK_ModRegs, MCK__41_, MCK__41_, MCK__61_, MCK_IntRegs, MCK__DOT_, MCK_new }, },
9984 { 205 /* memb */, Hexagon::S2_storerbnew_pci, Convert__Reg1_2__Tie0_0_0__s4_0Imm1_6__Reg1_10__Reg1_14, AMFBS_None, { MCK_memb, MCK__40_, MCK_IntRegs, MCK__43_, MCK__43_, MCK__HASH_, MCK_s4_0Imm, MCK__COLON_, MCK_circ, MCK__40_, MCK_ModRegs, MCK__41_, MCK__41_, MCK__61_, MCK_IntRegs, MCK__DOT_, MCK_new }, },
9985 { 210 /* memcpy */, Hexagon::L6_memcpy, Convert__Reg1_2__Reg1_3__Reg1_4, AMFBS_HasV66, { MCK_memcpy, MCK__40_, MCK_IntRegs, MCK_IntRegs, MCK_ModRegs, MCK__41_ }, },
9990 { 217 /* memd */, Hexagon::S2_storerd_pr, Convert__Reg1_2__Tie0_0_0__Reg1_5__Reg1_8, AMFBS_None, { MCK_memd, MCK__40_, MCK_IntRegs, MCK__43_, MCK__43_, MCK_ModRegs, MCK__41_, MCK__61_, MCK_DoubleRegs }, },
9993 { 217 /* memd */, Hexagon::S2_storerd_pbr, Convert__Reg1_2__Tie0_0_0__Reg1_5__Reg1_10, AMFBS_None, { MCK_memd, MCK__40_, MCK_IntRegs, MCK__43_, MCK__43_, MCK_ModRegs, MCK__COLON_, MCK_brev, MCK__41_, MCK__61_, MCK_DoubleRegs }, },
9996 { 217 /* memd */, Hexagon::S2_storerd_pcr, Convert__Reg1_2__Tie0_0_0__Reg1_9__Reg1_13, AMFBS_None, { MCK_memd, MCK__40_, MCK_IntRegs, MCK__43_, MCK__43_, MCK_I, MCK__COLON_, MCK_circ, MCK__40_, MCK_ModRegs, MCK__41_, MCK__41_, MCK__61_, MCK_DoubleRegs }, },
9997 { 217 /* memd */, Hexagon::S2_storerd_pci, Convert__Reg1_2__Tie0_0_0__s4_3Imm1_6__Reg1_10__Reg1_14, AMFBS_None, { MCK_memd, MCK__40_, MCK_IntRegs, MCK__43_, MCK__43_, MCK__HASH_, MCK_s4_3Imm, MCK__COLON_, MCK_circ, MCK__40_, MCK_ModRegs, MCK__41_, MCK__41_, MCK__61_, MCK_DoubleRegs }, },
10014 { 234 /* memh */, Hexagon::S2_storerh_pr, Convert__Reg1_2__Tie0_0_0__Reg1_5__Reg1_8, AMFBS_None, { MCK_memh, MCK__40_, MCK_IntRegs, MCK__43_, MCK__43_, MCK_ModRegs, MCK__41_, MCK__61_, MCK_IntRegs }, },
10030 { 234 /* memh */, Hexagon::S2_storerf_pr, Convert__Reg1_2__Tie0_0_0__Reg1_5__Reg1_8, AMFBS_None, { MCK_memh, MCK__40_, MCK_IntRegs, MCK__43_, MCK__43_, MCK_ModRegs, MCK__41_, MCK__61_, MCK_IntRegs, MCK__DOT_, MCK_h }, },
10031 { 234 /* memh */, Hexagon::S2_storerhnew_pr, Convert__Reg1_2__Tie0_0_0__Reg1_5__Reg1_8, AMFBS_None, { MCK_memh, MCK__40_, MCK_IntRegs, MCK__43_, MCK__43_, MCK_ModRegs, MCK__41_, MCK__61_, MCK_IntRegs, MCK__DOT_, MCK_new }, },
10032 { 234 /* memh */, Hexagon::S2_storerh_pbr, Convert__Reg1_2__Tie0_0_0__Reg1_5__Reg1_10, AMFBS_None, { MCK_memh, MCK__40_, MCK_IntRegs, MCK__43_, MCK__43_, MCK_ModRegs, MCK__COLON_, MCK_brev, MCK__41_, MCK__61_, MCK_IntRegs }, },
10040 { 234 /* memh */, Hexagon::S2_storerf_pbr, Convert__Reg1_2__Tie0_0_0__Reg1_5__Reg1_10, AMFBS_None, { MCK_memh, MCK__40_, MCK_IntRegs, MCK__43_, MCK__43_, MCK_ModRegs, MCK__COLON_, MCK_brev, MCK__41_, MCK__61_, MCK_IntRegs, MCK__DOT_, MCK_h }, },
10041 { 234 /* memh */, Hexagon::S2_storerhnew_pbr, Convert__Reg1_2__Tie0_0_0__Reg1_5__Reg1_10, AMFBS_None, { MCK_memh, MCK__40_, MCK_IntRegs, MCK__43_, MCK__43_, MCK_ModRegs, MCK__COLON_, MCK_brev, MCK__41_, MCK__61_, MCK_IntRegs, MCK__DOT_, MCK_new }, },
10043 { 234 /* memh */, Hexagon::S2_storerh_pcr, Convert__Reg1_2__Tie0_0_0__Reg1_9__Reg1_13, AMFBS_None, { MCK_memh, MCK__40_, MCK_IntRegs, MCK__43_, MCK__43_, MCK_I, MCK__COLON_, MCK_circ, MCK__40_, MCK_ModRegs, MCK__41_, MCK__41_, MCK__61_, MCK_IntRegs }, },
10046 { 234 /* memh */, Hexagon::S2_storerh_pci, Convert__Reg1_2__Tie0_0_0__s4_1Imm1_6__Reg1_10__Reg1_14, AMFBS_None, { MCK_memh, MCK__40_, MCK_IntRegs, MCK__43_, MCK__43_, MCK__HASH_, MCK_s4_1Imm, MCK__COLON_, MCK_circ, MCK__40_, MCK_ModRegs, MCK__41_, MCK__41_, MCK__61_, MCK_IntRegs }, },
10049 { 234 /* memh */, Hexagon::S2_storerf_pcr, Convert__Reg1_2__Tie0_0_0__Reg1_9__Reg1_13, AMFBS_None, { MCK_memh, MCK__40_, MCK_IntRegs, MCK__43_, MCK__43_, MCK_I, MCK__COLON_, MCK_circ, MCK__40_, MCK_ModRegs, MCK__41_, MCK__41_, MCK__61_, MCK_IntRegs, MCK__DOT_, MCK_h }, },
10050 { 234 /* memh */, Hexagon::S2_storerhnew_pcr, Convert__Reg1_2__Tie0_0_0__Reg1_9__Reg1_13, AMFBS_None, { MCK_memh, MCK__40_, MCK_IntRegs, MCK__43_, MCK__43_, MCK_I, MCK__COLON_, MCK_circ, MCK__40_, MCK_ModRegs, MCK__41_, MCK__41_, MCK__61_, MCK_IntRegs, MCK__DOT_, MCK_new }, },
10051 { 234 /* memh */, Hexagon::S2_storerf_pci, Convert__Reg1_2__Tie0_0_0__s4_1Imm1_6__Reg1_10__Reg1_14, AMFBS_None, { MCK_memh, MCK__40_, MCK_IntRegs, MCK__43_, MCK__43_, MCK__HASH_, MCK_s4_1Imm, MCK__COLON_, MCK_circ, MCK__40_, MCK_ModRegs, MCK__41_, MCK__41_, MCK__61_, MCK_IntRegs, MCK__DOT_, MCK_h }, },
10052 { 234 /* memh */, Hexagon::S2_storerhnew_pci, Convert__Reg1_2__Tie0_0_0__s4_1Imm1_6__Reg1_10__Reg1_14, AMFBS_None, { MCK_memh, MCK__40_, MCK_IntRegs, MCK__43_, MCK__43_, MCK__HASH_, MCK_s4_1Imm, MCK__COLON_, MCK_circ, MCK__40_, MCK_ModRegs, MCK__41_, MCK__41_, MCK__61_, MCK_IntRegs, MCK__DOT_, MCK_new }, },
10066 { 239 /* memw */, Hexagon::S2_storeri_pr, Convert__Reg1_2__Tie0_0_0__Reg1_5__Reg1_8, AMFBS_None, { MCK_memw, MCK__40_, MCK_IntRegs, MCK__43_, MCK__43_, MCK_ModRegs, MCK__41_, MCK__61_, MCK_IntRegs }, },
10080 { 239 /* memw */, Hexagon::S2_storerinew_pr, Convert__Reg1_2__Tie0_0_0__Reg1_5__Reg1_8, AMFBS_None, { MCK_memw, MCK__40_, MCK_IntRegs, MCK__43_, MCK__43_, MCK_ModRegs, MCK__41_, MCK__61_, MCK_IntRegs, MCK__DOT_, MCK_new }, },
10081 { 239 /* memw */, Hexagon::S2_storeri_pbr, Convert__Reg1_2__Tie0_0_0__Reg1_5__Reg1_10, AMFBS_None, { MCK_memw, MCK__40_, MCK_IntRegs, MCK__43_, MCK__43_, MCK_ModRegs, MCK__COLON_, MCK_brev, MCK__41_, MCK__61_, MCK_IntRegs }, },
10087 { 239 /* memw */, Hexagon::S2_storerinew_pbr, Convert__Reg1_2__Tie0_0_0__Reg1_5__Reg1_10, AMFBS_None, { MCK_memw, MCK__40_, MCK_IntRegs, MCK__43_, MCK__43_, MCK_ModRegs, MCK__COLON_, MCK_brev, MCK__41_, MCK__61_, MCK_IntRegs, MCK__DOT_, MCK_new }, },
10089 { 239 /* memw */, Hexagon::S2_storeri_pcr, Convert__Reg1_2__Tie0_0_0__Reg1_9__Reg1_13, AMFBS_None, { MCK_memw, MCK__40_, MCK_IntRegs, MCK__43_, MCK__43_, MCK_I, MCK__COLON_, MCK_circ, MCK__40_, MCK_ModRegs, MCK__41_, MCK__41_, MCK__61_, MCK_IntRegs }, },
10091 { 239 /* memw */, Hexagon::S2_storeri_pci, Convert__Reg1_2__Tie0_0_0__s4_2Imm1_6__Reg1_10__Reg1_14, AMFBS_None, { MCK_memw, MCK__40_, MCK_IntRegs, MCK__43_, MCK__43_, MCK__HASH_, MCK_s4_2Imm, MCK__COLON_, MCK_circ, MCK__40_, MCK_ModRegs, MCK__41_, MCK__41_, MCK__61_, MCK_IntRegs }, },
10093 { 239 /* memw */, Hexagon::S2_storerinew_pcr, Convert__Reg1_2__Tie0_0_0__Reg1_9__Reg1_13, AMFBS_None, { MCK_memw, MCK__40_, MCK_IntRegs, MCK__43_, MCK__43_, MCK_I, MCK__COLON_, MCK_circ, MCK__40_, MCK_ModRegs, MCK__41_, MCK__41_, MCK__61_, MCK_IntRegs, MCK__DOT_, MCK_new }, },
10094 { 239 /* memw */, Hexagon::S2_storerinew_pci, Convert__Reg1_2__Tie0_0_0__s4_2Imm1_6__Reg1_10__Reg1_14, AMFBS_None, { MCK_memw, MCK__40_, MCK_IntRegs, MCK__43_, MCK__43_, MCK__HASH_, MCK_s4_2Imm, MCK__COLON_, MCK_circ, MCK__40_, MCK_ModRegs, MCK__41_, MCK__41_, MCK__61_, MCK_IntRegs, MCK__DOT_, MCK_new }, },
10189 { 312 /* vmem */, Hexagon::V6_vS32b_srls_ppu, Convert__Reg1_2__Tie0_0_0__Reg1_5, AMFBS_UseHVXV65, { MCK_vmem, MCK__40_, MCK_IntRegs, MCK__43_, MCK__43_, MCK_ModRegs, MCK__41_, MCK__COLON_, MCK_scatter_95_release }, },
10190 { 312 /* vmem */, Hexagon::V6_vS32b_ppu, Convert__Reg1_2__Tie0_0_0__Reg1_5__Reg1_8, AMFBS_UseHVXV60, { MCK_vmem, MCK__40_, MCK_IntRegs, MCK__43_, MCK__43_, MCK_ModRegs, MCK__41_, MCK__61_, MCK_HvxVR }, },
10196 { 312 /* vmem */, Hexagon::V6_vS32b_nt_ppu, Convert__Reg1_2__Tie0_0_0__Reg1_5__Reg1_10, AMFBS_UseHVXV60, { MCK_vmem, MCK__40_, MCK_IntRegs, MCK__43_, MCK__43_, MCK_ModRegs, MCK__41_, MCK__COLON_, MCK_nt, MCK__61_, MCK_HvxVR }, },
10197 { 312 /* vmem */, Hexagon::V6_vS32b_new_ppu, Convert__Reg1_2__Tie0_0_0__Reg1_5__Reg1_8, AMFBS_UseHVXV60, { MCK_vmem, MCK__40_, MCK_IntRegs, MCK__43_, MCK__43_, MCK_ModRegs, MCK__41_, MCK__61_, MCK_HvxVR, MCK__DOT_, MCK_new }, },
10201 { 312 /* vmem */, Hexagon::V6_vS32b_nt_new_ppu, Convert__Reg1_2__Tie0_0_0__Reg1_5__Reg1_10, AMFBS_UseHVXV60, { MCK_vmem, MCK__40_, MCK_IntRegs, MCK__43_, MCK__43_, MCK_ModRegs, MCK__41_, MCK__COLON_, MCK_nt, MCK__61_, MCK_HvxVR, MCK__DOT_, MCK_new }, },
10205 { 317 /* vmemu */, Hexagon::V6_vS32Ub_ppu, Convert__Reg1_2__Tie0_0_0__Reg1_5__Reg1_8, AMFBS_UseHVXV60, { MCK_vmemu, MCK__40_, MCK_IntRegs, MCK__43_, MCK__43_, MCK_ModRegs, MCK__41_, MCK__61_, MCK_HvxVR }, },
10207 { 323 /* vscatter */, Hexagon::V6_vscattermhw, Convert__Reg1_2__Reg1_3__Reg1_4__Reg1_11, AMFBS_UseHVXV65, { MCK_vscatter, MCK__40_, MCK_IntRegs, MCK_ModRegs, MCK_HvxWR, MCK__DOT_, MCK_w, MCK__41_, MCK__DOT_, MCK_h, MCK__61_, MCK_HvxVR }, },
10208 { 323 /* vscatter */, Hexagon::V6_vscattermhw, Convert__Reg1_2__Reg1_3__Reg1_4__Reg1_9, AMFBS_UseHVX, { MCK_vscatter, MCK__40_, MCK_IntRegs, MCK_ModRegs, MCK_HvxWR, MCK__DOT_, MCK_w, MCK__41_, MCK__61_, MCK_HvxVR, MCK__DOT_, MCK_h }, },
10209 { 323 /* vscatter */, Hexagon::V6_vscattermh, Convert__Reg1_2__Reg1_3__Reg1_4__Reg1_11, AMFBS_UseHVXV65, { MCK_vscatter, MCK__40_, MCK_IntRegs, MCK_ModRegs, MCK_HvxVR, MCK__DOT_, MCK_h, MCK__41_, MCK__DOT_, MCK_h, MCK__61_, MCK_HvxVR }, },
10210 { 323 /* vscatter */, Hexagon::V6_vscattermh, Convert__Reg1_2__Reg1_3__Reg1_4__Reg1_9, AMFBS_UseHVX, { MCK_vscatter, MCK__40_, MCK_IntRegs, MCK_ModRegs, MCK_HvxVR, MCK__DOT_, MCK_h, MCK__41_, MCK__61_, MCK_HvxVR, MCK__DOT_, MCK_h }, },
10211 { 323 /* vscatter */, Hexagon::V6_vscattermw, Convert__Reg1_2__Reg1_3__Reg1_4__Reg1_11, AMFBS_UseHVXV65, { MCK_vscatter, MCK__40_, MCK_IntRegs, MCK_ModRegs, MCK_HvxVR, MCK__DOT_, MCK_w, MCK__41_, MCK__DOT_, MCK_w, MCK__61_, MCK_HvxVR }, },
10212 { 323 /* vscatter */, Hexagon::V6_vscattermw, Convert__Reg1_2__Reg1_3__Reg1_4__Reg1_9, AMFBS_UseHVX, { MCK_vscatter, MCK__40_, MCK_IntRegs, MCK_ModRegs, MCK_HvxVR, MCK__DOT_, MCK_w, MCK__41_, MCK__61_, MCK_HvxVR, MCK__DOT_, MCK_w }, },
10213 { 323 /* vscatter */, Hexagon::V6_vscattermhw_add, Convert__Reg1_2__Reg1_3__Reg1_4__Reg1_10, AMFBS_UseHVX, { MCK_vscatter, MCK__40_, MCK_IntRegs, MCK_ModRegs, MCK_HvxWR, MCK__DOT_, MCK_w, MCK__41_, MCK__43_, MCK__61_, MCK_HvxVR, MCK__DOT_, MCK_h }, },
10214 { 323 /* vscatter */, Hexagon::V6_vscattermhw_add, Convert__Reg1_2__Reg1_3__Reg1_4__Reg1_12, AMFBS_UseHVXV65, { MCK_vscatter, MCK__40_, MCK_IntRegs, MCK_ModRegs, MCK_HvxWR, MCK__DOT_, MCK_w, MCK__41_, MCK__DOT_, MCK_h, MCK__43_, MCK__61_, MCK_HvxVR }, },
10215 { 323 /* vscatter */, Hexagon::V6_vscattermh_add, Convert__Reg1_2__Reg1_3__Reg1_4__Reg1_10, AMFBS_UseHVX, { MCK_vscatter, MCK__40_, MCK_IntRegs, MCK_ModRegs, MCK_HvxVR, MCK__DOT_, MCK_h, MCK__41_, MCK__43_, MCK__61_, MCK_HvxVR, MCK__DOT_, MCK_h }, },
10216 { 323 /* vscatter */, Hexagon::V6_vscattermh_add, Convert__Reg1_2__Reg1_3__Reg1_4__Reg1_12, AMFBS_UseHVXV65, { MCK_vscatter, MCK__40_, MCK_IntRegs, MCK_ModRegs, MCK_HvxVR, MCK__DOT_, MCK_h, MCK__41_, MCK__DOT_, MCK_h, MCK__43_, MCK__61_, MCK_HvxVR }, },
10217 { 323 /* vscatter */, Hexagon::V6_vscattermw_add, Convert__Reg1_2__Reg1_3__Reg1_4__Reg1_10, AMFBS_UseHVX, { MCK_vscatter, MCK__40_, MCK_IntRegs, MCK_ModRegs, MCK_HvxVR, MCK__DOT_, MCK_w, MCK__41_, MCK__43_, MCK__61_, MCK_HvxVR, MCK__DOT_, MCK_w }, },
10218 { 323 /* vscatter */, Hexagon::V6_vscattermw_add, Convert__Reg1_2__Reg1_3__Reg1_4__Reg1_12, AMFBS_UseHVXV65, { MCK_vscatter, MCK__40_, MCK_IntRegs, MCK_ModRegs, MCK_HvxVR, MCK__DOT_, MCK_w, MCK__41_, MCK__DOT_, MCK_w, MCK__43_, MCK__61_, MCK_HvxVR }, },
10220 { 339 /* vtmp */, Hexagon::V6_vgathermhw, Convert__Reg1_6__Reg1_7__Reg1_8, AMFBS_UseHVXV65, { MCK_V65Regs, MCK__DOT_, MCK_h, MCK__61_, MCK_vgather, MCK__40_, MCK_IntRegs, MCK_ModRegs, MCK_HvxWR, MCK__DOT_, MCK_w, MCK__41_, MCK__DOT_, MCK_h }, },
10221 { 339 /* vtmp */, Hexagon::V6_vgathermh, Convert__Reg1_6__Reg1_7__Reg1_8, AMFBS_UseHVXV65, { MCK_V65Regs, MCK__DOT_, MCK_h, MCK__61_, MCK_vgather, MCK__40_, MCK_IntRegs, MCK_ModRegs, MCK_HvxVR, MCK__DOT_, MCK_h, MCK__41_, MCK__DOT_, MCK_h }, },
10222 { 339 /* vtmp */, Hexagon::V6_vgathermw, Convert__Reg1_6__Reg1_7__Reg1_8, AMFBS_UseHVXV65, { MCK_V65Regs, MCK__DOT_, MCK_w, MCK__61_, MCK_vgather, MCK__40_, MCK_IntRegs, MCK_ModRegs, MCK_HvxVR, MCK__DOT_, MCK_w, MCK__41_, MCK__DOT_, MCK_w }, },
10235 { 379 /* z */, Hexagon::V6_zLd_ppu, Convert__Reg1_4__Tie0_0_0__Reg1_7, AMFBS_UseHVXV66_UseZReg, { MCK_z, MCK__61_, MCK_vmem, MCK__40_, MCK_IntRegs, MCK__43_, MCK__43_, MCK_ModRegs, MCK__41_ }, },