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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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References
gen/lib/Target/Hexagon/HexagonGenAsmMatcher.inc 9956 { 205 /* memb */, Hexagon::S2_storerb_pr, Convert__Reg1_2__Tie0_0_0__Reg1_5__Reg1_8, AMFBS_None, { MCK_memb, MCK__40_, MCK_IntRegs, MCK__43_, MCK__43_, MCK_ModRegs, MCK__41_, MCK__61_, MCK_IntRegs }, },
9970 { 205 /* memb */, Hexagon::S2_storerbnew_pr, Convert__Reg1_2__Tie0_0_0__Reg1_5__Reg1_8, AMFBS_None, { MCK_memb, MCK__40_, MCK_IntRegs, MCK__43_, MCK__43_, MCK_ModRegs, MCK__41_, MCK__61_, MCK_IntRegs, MCK__DOT_, MCK_new }, },
9990 { 217 /* memd */, Hexagon::S2_storerd_pr, Convert__Reg1_2__Tie0_0_0__Reg1_5__Reg1_8, AMFBS_None, { MCK_memd, MCK__40_, MCK_IntRegs, MCK__43_, MCK__43_, MCK_ModRegs, MCK__41_, MCK__61_, MCK_DoubleRegs }, },
10014 { 234 /* memh */, Hexagon::S2_storerh_pr, Convert__Reg1_2__Tie0_0_0__Reg1_5__Reg1_8, AMFBS_None, { MCK_memh, MCK__40_, MCK_IntRegs, MCK__43_, MCK__43_, MCK_ModRegs, MCK__41_, MCK__61_, MCK_IntRegs }, },
10030 { 234 /* memh */, Hexagon::S2_storerf_pr, Convert__Reg1_2__Tie0_0_0__Reg1_5__Reg1_8, AMFBS_None, { MCK_memh, MCK__40_, MCK_IntRegs, MCK__43_, MCK__43_, MCK_ModRegs, MCK__41_, MCK__61_, MCK_IntRegs, MCK__DOT_, MCK_h }, },
10031 { 234 /* memh */, Hexagon::S2_storerhnew_pr, Convert__Reg1_2__Tie0_0_0__Reg1_5__Reg1_8, AMFBS_None, { MCK_memh, MCK__40_, MCK_IntRegs, MCK__43_, MCK__43_, MCK_ModRegs, MCK__41_, MCK__61_, MCK_IntRegs, MCK__DOT_, MCK_new }, },
10066 { 239 /* memw */, Hexagon::S2_storeri_pr, Convert__Reg1_2__Tie0_0_0__Reg1_5__Reg1_8, AMFBS_None, { MCK_memw, MCK__40_, MCK_IntRegs, MCK__43_, MCK__43_, MCK_ModRegs, MCK__41_, MCK__61_, MCK_IntRegs }, },
10080 { 239 /* memw */, Hexagon::S2_storerinew_pr, Convert__Reg1_2__Tie0_0_0__Reg1_5__Reg1_8, AMFBS_None, { MCK_memw, MCK__40_, MCK_IntRegs, MCK__43_, MCK__43_, MCK_ModRegs, MCK__41_, MCK__61_, MCK_IntRegs, MCK__DOT_, MCK_new }, },
10190 { 312 /* vmem */, Hexagon::V6_vS32b_ppu, Convert__Reg1_2__Tie0_0_0__Reg1_5__Reg1_8, AMFBS_UseHVXV60, { MCK_vmem, MCK__40_, MCK_IntRegs, MCK__43_, MCK__43_, MCK_ModRegs, MCK__41_, MCK__61_, MCK_HvxVR }, },
10197 { 312 /* vmem */, Hexagon::V6_vS32b_new_ppu, Convert__Reg1_2__Tie0_0_0__Reg1_5__Reg1_8, AMFBS_UseHVXV60, { MCK_vmem, MCK__40_, MCK_IntRegs, MCK__43_, MCK__43_, MCK_ModRegs, MCK__41_, MCK__61_, MCK_HvxVR, MCK__DOT_, MCK_new }, },
10205 { 317 /* vmemu */, Hexagon::V6_vS32Ub_ppu, Convert__Reg1_2__Tie0_0_0__Reg1_5__Reg1_8, AMFBS_UseHVXV60, { MCK_vmemu, MCK__40_, MCK_IntRegs, MCK__43_, MCK__43_, MCK_ModRegs, MCK__41_, MCK__61_, MCK_HvxVR }, },