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reference to multiple definitions → definitions
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References

gen/lib/Target/Hexagon/HexagonGenAsmMatcher.inc
 8824   { 0 /*  */, Hexagon::S4_addi_asl_ri, Convert__Reg1_0__u32_0Imm1_5__Tie0_0_8__u5_0Imm1_10, AMFBS_None, { MCK_IntRegs, MCK__61_, MCK_add, MCK__40_, MCK__HASH_, MCK_u32_0Imm, MCK_asl, MCK__40_, MCK_IntRegs, MCK__HASH_, MCK_u5_0Imm, MCK__41_, MCK__41_ }, },
 8825   { 0 /*  */, Hexagon::S4_addi_lsr_ri, Convert__Reg1_0__u32_0Imm1_5__Tie0_0_8__u5_0Imm1_10, AMFBS_None, { MCK_IntRegs, MCK__61_, MCK_add, MCK__40_, MCK__HASH_, MCK_u32_0Imm, MCK_lsr, MCK__40_, MCK_IntRegs, MCK__HASH_, MCK_u5_0Imm, MCK__41_, MCK__41_ }, },
 8829   { 0 /*  */, Hexagon::S4_andi_asl_ri, Convert__Reg1_0__u32_0Imm1_5__Tie0_0_8__u5_0Imm1_10, AMFBS_None, { MCK_IntRegs, MCK__61_, MCK_and, MCK__40_, MCK__HASH_, MCK_u32_0Imm, MCK_asl, MCK__40_, MCK_IntRegs, MCK__HASH_, MCK_u5_0Imm, MCK__41_, MCK__41_ }, },
 8830   { 0 /*  */, Hexagon::S4_andi_lsr_ri, Convert__Reg1_0__u32_0Imm1_5__Tie0_0_8__u5_0Imm1_10, AMFBS_None, { MCK_IntRegs, MCK__61_, MCK_and, MCK__40_, MCK__HASH_, MCK_u32_0Imm, MCK_lsr, MCK__40_, MCK_IntRegs, MCK__HASH_, MCK_u5_0Imm, MCK__41_, MCK__41_ }, },
 8847   { 0 /*  */, Hexagon::S4_ori_asl_ri, Convert__Reg1_0__u32_0Imm1_5__Tie0_0_8__u5_0Imm1_10, AMFBS_None, { MCK_IntRegs, MCK__61_, MCK_or, MCK__40_, MCK__HASH_, MCK_u32_0Imm, MCK_asl, MCK__40_, MCK_IntRegs, MCK__HASH_, MCK_u5_0Imm, MCK__41_, MCK__41_ }, },
 8848   { 0 /*  */, Hexagon::S4_ori_lsr_ri, Convert__Reg1_0__u32_0Imm1_5__Tie0_0_8__u5_0Imm1_10, AMFBS_None, { MCK_IntRegs, MCK__61_, MCK_or, MCK__40_, MCK__HASH_, MCK_u32_0Imm, MCK_lsr, MCK__40_, MCK_IntRegs, MCK__HASH_, MCK_u5_0Imm, MCK__41_, MCK__41_ }, },
 8849   { 0 /*  */, Hexagon::S4_subi_asl_ri, Convert__Reg1_0__u32_0Imm1_5__Tie0_0_8__u5_0Imm1_10, AMFBS_None, { MCK_IntRegs, MCK__61_, MCK_sub, MCK__40_, MCK__HASH_, MCK_u32_0Imm, MCK_asl, MCK__40_, MCK_IntRegs, MCK__HASH_, MCK_u5_0Imm, MCK__41_, MCK__41_ }, },
 8850   { 0 /*  */, Hexagon::S4_subi_lsr_ri, Convert__Reg1_0__u32_0Imm1_5__Tie0_0_8__u5_0Imm1_10, AMFBS_None, { MCK_IntRegs, MCK__61_, MCK_sub, MCK__40_, MCK__HASH_, MCK_u32_0Imm, MCK_lsr, MCK__40_, MCK_IntRegs, MCK__HASH_, MCK_u5_0Imm, MCK__41_, MCK__41_ }, },