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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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References
gen/lib/Target/Hexagon/HexagonGenAsmMatcher.inc 7757 { 0 /* */, Hexagon::S2_insertp_rp, Convert__Reg1_0__Tie0_0_0__Reg1_4__Reg1_5, AMFBS_None, { MCK_DoubleRegs, MCK__61_, MCK_insert, MCK__40_, MCK_DoubleRegs, MCK_DoubleRegs, MCK__41_ }, },
7819 { 0 /* */, Hexagon::A4_vrmaxh, Convert__Reg1_0__Tie0_0_0__Reg1_4__Reg1_5, AMFBS_None, { MCK_DoubleRegs, MCK__61_, MCK_vrmaxh, MCK__40_, MCK_DoubleRegs, MCK_IntRegs, MCK__41_ }, },
7820 { 0 /* */, Hexagon::A4_vrmaxuh, Convert__Reg1_0__Tie0_0_0__Reg1_4__Reg1_5, AMFBS_None, { MCK_DoubleRegs, MCK__61_, MCK_vrmaxuh, MCK__40_, MCK_DoubleRegs, MCK_IntRegs, MCK__41_ }, },
7821 { 0 /* */, Hexagon::A4_vrmaxuw, Convert__Reg1_0__Tie0_0_0__Reg1_4__Reg1_5, AMFBS_None, { MCK_DoubleRegs, MCK__61_, MCK_vrmaxuw, MCK__40_, MCK_DoubleRegs, MCK_IntRegs, MCK__41_ }, },
7822 { 0 /* */, Hexagon::A4_vrmaxw, Convert__Reg1_0__Tie0_0_0__Reg1_4__Reg1_5, AMFBS_None, { MCK_DoubleRegs, MCK__61_, MCK_vrmaxw, MCK__40_, MCK_DoubleRegs, MCK_IntRegs, MCK__41_ }, },
7823 { 0 /* */, Hexagon::A4_vrminh, Convert__Reg1_0__Tie0_0_0__Reg1_4__Reg1_5, AMFBS_None, { MCK_DoubleRegs, MCK__61_, MCK_vrminh, MCK__40_, MCK_DoubleRegs, MCK_IntRegs, MCK__41_ }, },
7824 { 0 /* */, Hexagon::A4_vrminuh, Convert__Reg1_0__Tie0_0_0__Reg1_4__Reg1_5, AMFBS_None, { MCK_DoubleRegs, MCK__61_, MCK_vrminuh, MCK__40_, MCK_DoubleRegs, MCK_IntRegs, MCK__41_ }, },
7825 { 0 /* */, Hexagon::A4_vrminuw, Convert__Reg1_0__Tie0_0_0__Reg1_4__Reg1_5, AMFBS_None, { MCK_DoubleRegs, MCK__61_, MCK_vrminuw, MCK__40_, MCK_DoubleRegs, MCK_IntRegs, MCK__41_ }, },
7826 { 0 /* */, Hexagon::A4_vrminw, Convert__Reg1_0__Tie0_0_0__Reg1_4__Reg1_5, AMFBS_None, { MCK_DoubleRegs, MCK__61_, MCK_vrminw, MCK__40_, MCK_DoubleRegs, MCK_IntRegs, MCK__41_ }, },
7849 { 0 /* */, Hexagon::V6_vasr_into, Convert__Reg1_0__Tie0_0_0__Reg1_4__Reg1_5, AMFBS_UseHVX, { MCK_HvxWR, MCK__61_, MCK_vasrinto, MCK__40_, MCK_HvxVR, MCK_HvxVR, MCK__41_ }, },
7893 { 0 /* */, Hexagon::S2_insert_rp, Convert__Reg1_0__Tie0_0_0__Reg1_4__Reg1_5, AMFBS_None, { MCK_IntRegs, MCK__61_, MCK_insert, MCK__40_, MCK_IntRegs, MCK_DoubleRegs, MCK__41_ }, },