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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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References
gen/lib/Target/Hexagon/HexagonGenAsmMatcher.inc 8023 { 0 /* */, Hexagon::F2_dfclass, Convert__Reg1_0__Reg1_4__u5_0Imm1_6, AMFBS_None, { MCK_PredRegs, MCK__61_, MCK_dfclass, MCK__40_, MCK_DoubleRegs, MCK__HASH_, MCK_u5_0Imm, MCK__41_ }, },
8025 { 0 /* */, Hexagon::F2_sfclass, Convert__Reg1_0__Reg1_4__u5_0Imm1_6, AMFBS_None, { MCK_PredRegs, MCK__61_, MCK_sfclass, MCK__40_, MCK_IntRegs, MCK__HASH_, MCK_u5_0Imm, MCK__41_ }, },
8026 { 0 /* */, Hexagon::S2_tstbit_i, Convert__Reg1_0__Reg1_4__u5_0Imm1_6, AMFBS_None, { MCK_PredRegs, MCK__61_, MCK_tstbit, MCK__40_, MCK_IntRegs, MCK__HASH_, MCK_u5_0Imm, MCK__41_ }, },
8063 { 0 /* */, Hexagon::A4_bitspliti, Convert__Reg1_0__Reg1_4__u5_0Imm1_6, AMFBS_None, { MCK_DoubleRegs, MCK__61_, MCK_bitsplit, MCK__40_, MCK_IntRegs, MCK__HASH_, MCK_u5_0Imm, MCK__41_ }, },
8079 { 0 /* */, Hexagon::S2_asl_i_vw, Convert__Reg1_0__Reg1_4__u5_0Imm1_6, AMFBS_None, { MCK_DoubleRegs, MCK__61_, MCK_vaslw, MCK__40_, MCK_DoubleRegs, MCK__HASH_, MCK_u5_0Imm, MCK__41_ }, },
8081 { 0 /* */, Hexagon::S2_asr_i_vw, Convert__Reg1_0__Reg1_4__u5_0Imm1_6, AMFBS_None, { MCK_DoubleRegs, MCK__61_, MCK_vasrw, MCK__40_, MCK_DoubleRegs, MCK__HASH_, MCK_u5_0Imm, MCK__41_ }, },
8084 { 0 /* */, Hexagon::S2_lsr_i_vw, Convert__Reg1_0__Reg1_4__u5_0Imm1_6, AMFBS_None, { MCK_DoubleRegs, MCK__61_, MCK_vlsrw, MCK__40_, MCK_DoubleRegs, MCK__HASH_, MCK_u5_0Imm, MCK__41_ }, },
8155 { 0 /* */, Hexagon::S2_asl_i_r, Convert__Reg1_0__Reg1_4__u5_0Imm1_6, AMFBS_None, { MCK_IntRegs, MCK__61_, MCK_asl, MCK__40_, MCK_IntRegs, MCK__HASH_, MCK_u5_0Imm, MCK__41_ }, },
8156 { 0 /* */, Hexagon::S2_asr_i_r, Convert__Reg1_0__Reg1_4__u5_0Imm1_6, AMFBS_None, { MCK_IntRegs, MCK__61_, MCK_asr, MCK__40_, MCK_IntRegs, MCK__HASH_, MCK_u5_0Imm, MCK__41_ }, },
8157 { 0 /* */, Hexagon::S2_asr_i_r_rnd_goodsyntax, Convert__Reg1_0__Reg1_4__u5_0Imm1_6, AMFBS_None, { MCK_IntRegs, MCK__61_, MCK_asrrnd, MCK__40_, MCK_IntRegs, MCK__HASH_, MCK_u5_0Imm, MCK__41_ }, },
8158 { 0 /* */, Hexagon::S2_clrbit_i, Convert__Reg1_0__Reg1_4__u5_0Imm1_6, AMFBS_None, { MCK_IntRegs, MCK__61_, MCK_clrbit, MCK__40_, MCK_IntRegs, MCK__HASH_, MCK_u5_0Imm, MCK__41_ }, },
8163 { 0 /* */, Hexagon::A4_cround_ri, Convert__Reg1_0__Reg1_4__u5_0Imm1_6, AMFBS_None, { MCK_IntRegs, MCK__61_, MCK_cround, MCK__40_, MCK_IntRegs, MCK__HASH_, MCK_u5_0Imm, MCK__41_ }, },
8165 { 0 /* */, Hexagon::S2_lsr_i_r, Convert__Reg1_0__Reg1_4__u5_0Imm1_6, AMFBS_None, { MCK_IntRegs, MCK__61_, MCK_lsr, MCK__40_, MCK_IntRegs, MCK__HASH_, MCK_u5_0Imm, MCK__41_ }, },
8171 { 0 /* */, Hexagon::S6_rol_i_r, Convert__Reg1_0__Reg1_4__u5_0Imm1_6, AMFBS_HasV60, { MCK_IntRegs, MCK__61_, MCK_rol, MCK__40_, MCK_IntRegs, MCK__HASH_, MCK_u5_0Imm, MCK__41_ }, },
8173 { 0 /* */, Hexagon::A4_round_ri, Convert__Reg1_0__Reg1_4__u5_0Imm1_6, AMFBS_None, { MCK_IntRegs, MCK__61_, MCK_round, MCK__40_, MCK_IntRegs, MCK__HASH_, MCK_u5_0Imm, MCK__41_ }, },
8174 { 0 /* */, Hexagon::S2_setbit_i, Convert__Reg1_0__Reg1_4__u5_0Imm1_6, AMFBS_None, { MCK_IntRegs, MCK__61_, MCK_setbit, MCK__40_, MCK_IntRegs, MCK__HASH_, MCK_u5_0Imm, MCK__41_ }, },
8176 { 0 /* */, Hexagon::S2_togglebit_i, Convert__Reg1_0__Reg1_4__u5_0Imm1_6, AMFBS_None, { MCK_IntRegs, MCK__61_, MCK_togglebit, MCK__40_, MCK_IntRegs, MCK__HASH_, MCK_u5_0Imm, MCK__41_ }, },
8177 { 0 /* */, Hexagon::S2_asr_i_svw_trun, Convert__Reg1_0__Reg1_4__u5_0Imm1_6, AMFBS_None, { MCK_IntRegs, MCK__61_, MCK_vasrw, MCK__40_, MCK_DoubleRegs, MCK__HASH_, MCK_u5_0Imm, MCK__41_ }, },
8533 { 0 /* */, Hexagon::S2_asl_i_r_sat, Convert__Reg1_0__Reg1_4__u5_0Imm1_6, AMFBS_None, { MCK_IntRegs, MCK__61_, MCK_asl, MCK__40_, MCK_IntRegs, MCK__HASH_, MCK_u5_0Imm, MCK__41_, MCK__COLON_, MCK_sat }, },
8534 { 0 /* */, Hexagon::S2_asr_i_r_rnd, Convert__Reg1_0__Reg1_4__u5_0Imm1_6, AMFBS_None, { MCK_IntRegs, MCK__61_, MCK_asr, MCK__40_, MCK_IntRegs, MCK__HASH_, MCK_u5_0Imm, MCK__41_, MCK__COLON_, MCK_rnd }, },
8547 { 0 /* */, Hexagon::A4_round_ri_sat, Convert__Reg1_0__Reg1_4__u5_0Imm1_6, AMFBS_None, { MCK_IntRegs, MCK__61_, MCK_round, MCK__40_, MCK_IntRegs, MCK__HASH_, MCK_u5_0Imm, MCK__41_, MCK__COLON_, MCK_sat }, },