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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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References
gen/lib/Target/Hexagon/HexagonGenAsmMatcher.inc 8077 { 0 /* */, Hexagon::S2_valignrb, Convert__Reg1_0__Reg1_4__Reg1_5__Reg1_6, AMFBS_None, { MCK_DoubleRegs, MCK__61_, MCK_valignb, MCK__40_, MCK_DoubleRegs, MCK_DoubleRegs, MCK_PredRegs, MCK__41_ }, },
8085 { 0 /* */, Hexagon::C2_vmux, Convert__Reg1_0__Reg1_4__Reg1_5__Reg1_6, AMFBS_None, { MCK_DoubleRegs, MCK__61_, MCK_vmux, MCK__40_, MCK_PredRegs, MCK_DoubleRegs, MCK_DoubleRegs, MCK__41_ }, },
8088 { 0 /* */, Hexagon::S2_vsplicerb, Convert__Reg1_0__Reg1_4__Reg1_5__Reg1_6, AMFBS_None, { MCK_DoubleRegs, MCK__61_, MCK_vspliceb, MCK__40_, MCK_DoubleRegs, MCK_DoubleRegs, MCK_PredRegs, MCK__41_ }, },
8125 { 0 /* */, Hexagon::V6_vdealvdd, Convert__Reg1_0__Reg1_4__Reg1_5__Reg1_6, AMFBS_UseHVXV60, { MCK_HvxWR, MCK__61_, MCK_vdeal, MCK__40_, MCK_HvxVR, MCK_HvxVR, MCK_IntRegsLow8, MCK__41_ }, },
8126 { 0 /* */, Hexagon::V6_vshuffvdd, Convert__Reg1_0__Reg1_4__Reg1_5__Reg1_6, AMFBS_UseHVXV60, { MCK_HvxWR, MCK__61_, MCK_vshuff, MCK__40_, MCK_HvxVR, MCK_HvxVR, MCK_IntRegsLow8, MCK__41_ }, },
8127 { 0 /* */, Hexagon::V6_vswap, Convert__Reg1_0__Reg1_4__Reg1_5__Reg1_6, AMFBS_UseHVXV60, { MCK_HvxWR, MCK__61_, MCK_vswap, MCK__40_, MCK_HvxQR, MCK_HvxVR, MCK_HvxVR, MCK__41_ }, },
8167 { 0 /* */, Hexagon::C2_mux, Convert__Reg1_0__Reg1_4__Reg1_5__Reg1_6, AMFBS_None, { MCK_IntRegs, MCK__61_, MCK_mux, MCK__40_, MCK_PredRegs, MCK_IntRegs, MCK_IntRegs, MCK__41_ }, },
8217 { 0 /* */, Hexagon::V6_valignb, Convert__Reg1_0__Reg1_4__Reg1_5__Reg1_6, AMFBS_UseHVXV60, { MCK_HvxVR, MCK__61_, MCK_valign, MCK__40_, MCK_HvxVR, MCK_HvxVR, MCK_IntRegsLow8, MCK__41_ }, },
8220 { 0 /* */, Hexagon::V6_vasrwhsat, Convert__Reg1_0__Reg1_4__Reg1_5__Reg1_6, AMFBS_None, { MCK_HvxVR, MCK__61_, MCK_vasrwh, MCK__40_, MCK_HvxVR, MCK_HvxVR, MCK_IntRegsLow8, MCK__41_ }, },
8221 { 0 /* */, Hexagon::V6_vlalignb, Convert__Reg1_0__Reg1_4__Reg1_5__Reg1_6, AMFBS_UseHVXV60, { MCK_HvxVR, MCK__61_, MCK_vlalign, MCK__40_, MCK_HvxVR, MCK_HvxVR, MCK_IntRegsLow8, MCK__41_ }, },
8224 { 0 /* */, Hexagon::V6_vmux, Convert__Reg1_0__Reg1_4__Reg1_5__Reg1_6, AMFBS_UseHVXV60, { MCK_HvxVR, MCK__61_, MCK_vmux, MCK__40_, MCK_HvxQR, MCK_HvxVR, MCK_HvxVR, MCK__41_ }, },
8573 { 0 /* */, Hexagon::V6_vasrhubsat, Convert__Reg1_0__Reg1_4__Reg1_5__Reg1_6, AMFBS_None, { MCK_HvxVR, MCK__61_, MCK_vasrhub, MCK__40_, MCK_HvxVR, MCK_HvxVR, MCK_IntRegsLow8, MCK__41_, MCK__COLON_, MCK_sat }, },
8574 { 0 /* */, Hexagon::V6_vasrwhsat, Convert__Reg1_0__Reg1_4__Reg1_5__Reg1_6, AMFBS_None, { MCK_HvxVR, MCK__61_, MCK_vasrwh, MCK__40_, MCK_HvxVR, MCK_HvxVR, MCK_IntRegsLow8, MCK__41_, MCK__COLON_, MCK_sat }, },
8575 { 0 /* */, Hexagon::V6_vasrwuhsat, Convert__Reg1_0__Reg1_4__Reg1_5__Reg1_6, AMFBS_None, { MCK_HvxVR, MCK__61_, MCK_vasrwuh, MCK__40_, MCK_HvxVR, MCK_HvxVR, MCK_IntRegsLow8, MCK__41_, MCK__COLON_, MCK_sat }, },
8737 { 0 /* */, Hexagon::V6_vasrhbrndsat, Convert__Reg1_0__Reg1_4__Reg1_5__Reg1_6, AMFBS_None, { MCK_HvxVR, MCK__61_, MCK_vasrhb, MCK__40_, MCK_HvxVR, MCK_HvxVR, MCK_IntRegsLow8, MCK__41_, MCK__COLON_, MCK_rnd, MCK__COLON_, MCK_sat }, },
8738 { 0 /* */, Hexagon::V6_vasrhubrndsat, Convert__Reg1_0__Reg1_4__Reg1_5__Reg1_6, AMFBS_None, { MCK_HvxVR, MCK__61_, MCK_vasrhub, MCK__40_, MCK_HvxVR, MCK_HvxVR, MCK_IntRegsLow8, MCK__41_, MCK__COLON_, MCK_rnd, MCK__COLON_, MCK_sat }, },
8739 { 0 /* */, Hexagon::V6_vasrwhrndsat, Convert__Reg1_0__Reg1_4__Reg1_5__Reg1_6, AMFBS_None, { MCK_HvxVR, MCK__61_, MCK_vasrwh, MCK__40_, MCK_HvxVR, MCK_HvxVR, MCK_IntRegsLow8, MCK__41_, MCK__COLON_, MCK_rnd, MCK__COLON_, MCK_sat }, },