reference, declaration → definition definition → references, declarations, derived classes, virtual overrides reference to multiple definitions → definitions unreferenced |
436 tmp = fieldFromInstruction(insn, 4, 5); 437 if (DecodeGPR8RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; } 438 tmp = 0x0; 439 tmp |= fieldFromInstruction(insn, 0, 4) << 0; 440 tmp |= fieldFromInstruction(insn, 9, 1) << 4; 441 if (DecodeGPR8RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; } 444 tmp = fieldFromInstruction(insn, 4, 5); 445 if (DecodeGPR8RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; } 446 tmp = fieldFromInstruction(insn, 4, 5); 447 if (DecodeGPR8RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; } 448 tmp = 0x0; 449 tmp |= fieldFromInstruction(insn, 0, 4) << 0; 450 tmp |= fieldFromInstruction(insn, 9, 1) << 4; 451 if (DecodeGPR8RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; } 454 tmp = fieldFromInstruction(insn, 4, 4); 455 if (DecodeLD8RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; } 456 tmp = 0x0; 457 tmp |= fieldFromInstruction(insn, 0, 4) << 0; 458 tmp |= fieldFromInstruction(insn, 8, 4) << 4; 459 MI.addOperand(MCOperand::createImm(tmp)); 462 tmp = fieldFromInstruction(insn, 4, 4); 463 if (DecodeLD8RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; } 464 tmp = fieldFromInstruction(insn, 4, 4); 465 if (DecodeLD8RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; } 466 tmp = 0x0; 467 tmp |= fieldFromInstruction(insn, 0, 4) << 0; 468 tmp |= fieldFromInstruction(insn, 8, 4) << 4; 469 MI.addOperand(MCOperand::createImm(tmp)); 472 tmp = fieldFromInstruction(insn, 4, 5); 473 if (DecodeGPR8RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; } 474 tmp = fieldFromInstruction(insn, 2, 2); 475 MI.addOperand(MCOperand::createImm(tmp)); 478 tmp = fieldFromInstruction(insn, 4, 5); 479 if (DecodeGPR8RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; } 480 tmp = fieldFromInstruction(insn, 2, 2); 481 if (DecodePTRREGSRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; } 482 tmp = fieldFromInstruction(insn, 2, 2); 483 MI.addOperand(MCOperand::createImm(tmp)); 486 tmp = fieldFromInstruction(insn, 4, 5); 487 if (DecodeGPR8RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; } 488 tmp = 0x0; 489 tmp |= fieldFromInstruction(insn, 0, 3) << 0; 490 tmp |= fieldFromInstruction(insn, 3, 1) << 6; 491 tmp |= fieldFromInstruction(insn, 10, 2) << 3; 492 tmp |= fieldFromInstruction(insn, 13, 1) << 5; 493 MI.addOperand(MCOperand::createImm(tmp)); 496 tmp = fieldFromInstruction(insn, 2, 2); 497 MI.addOperand(MCOperand::createImm(tmp)); 498 tmp = fieldFromInstruction(insn, 4, 5); 499 if (DecodeGPR8RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; } 502 tmp = fieldFromInstruction(insn, 2, 2); 503 MI.addOperand(MCOperand::createImm(tmp)); 504 tmp = fieldFromInstruction(insn, 2, 2); 505 MI.addOperand(MCOperand::createImm(tmp)); 506 tmp = fieldFromInstruction(insn, 4, 5); 507 if (DecodeGPR8RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; } 510 tmp = 0x0; 511 tmp |= fieldFromInstruction(insn, 0, 3) << 0; 512 tmp |= fieldFromInstruction(insn, 3, 1) << 6; 513 tmp |= fieldFromInstruction(insn, 10, 2) << 3; 514 tmp |= fieldFromInstruction(insn, 13, 1) << 5; 515 MI.addOperand(MCOperand::createImm(tmp)); 516 tmp = fieldFromInstruction(insn, 4, 5); 517 if (DecodeGPR8RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; } 520 tmp = fieldFromInstruction(insn, 4, 5); 521 if (DecodeGPR8RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; } 524 tmp = fieldFromInstruction(insn, 4, 3); 525 MI.addOperand(MCOperand::createImm(tmp)); 528 tmp = fieldFromInstruction(insn, 4, 4); 529 MI.addOperand(MCOperand::createImm(tmp)); 532 tmp = 0x0; 533 tmp |= fieldFromInstruction(insn, 0, 4) << 0; 534 tmp |= fieldFromInstruction(insn, 6, 2) << 4; 535 MI.addOperand(MCOperand::createImm(tmp)); 538 tmp = fieldFromInstruction(insn, 0, 3); 539 MI.addOperand(MCOperand::createImm(tmp)); 542 tmp = fieldFromInstruction(insn, 0, 3); 543 MI.addOperand(MCOperand::createImm(tmp)); 544 tmp = fieldFromInstruction(insn, 3, 7); 545 MI.addOperand(MCOperand::createImm(tmp)); 548 tmp = fieldFromInstruction(insn, 4, 5); 549 if (DecodeGPR8RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; } 550 tmp = fieldFromInstruction(insn, 0, 3); 551 MI.addOperand(MCOperand::createImm(tmp)); 554 tmp = fieldFromInstruction(insn, 20, 5); 555 if (DecodeGPR8RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; } 556 tmp = fieldFromInstruction(insn, 0, 16); 557 MI.addOperand(MCOperand::createImm(tmp)); 560 tmp = fieldFromInstruction(insn, 0, 16); 561 MI.addOperand(MCOperand::createImm(tmp)); 562 tmp = fieldFromInstruction(insn, 20, 5); 563 if (DecodeGPR8RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; } 566 tmp = 0x0; 567 tmp |= fieldFromInstruction(insn, 0, 17) << 0; 568 tmp |= fieldFromInstruction(insn, 20, 5) << 17; 569 MI.addOperand(MCOperand::createImm(tmp));