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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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References
gen/lib/Target/ARM/ARMGenAsmMatcher.inc 9792 if ((FB[ARM::HasV8Ops]))
9794 if ((!FB[ARM::HasV8Ops]))
gen/lib/Target/ARM/ARMGenAsmWriter.inc12142 STI.getFeatureBits()[ARM::HasV8Ops]) {
12716 STI.getFeatureBits()[ARM::HasV8Ops]) {
12804 STI.getFeatureBits()[ARM::HasV8Ops]) {
gen/lib/Target/ARM/ARMGenDisassemblerTables.inc16579 return (!Bits[ARM::ModeThumb] && Bits[ARM::HasV8Ops] && Bits[ARM::FeatureCRC]);
16583 return (!Bits[ARM::ModeThumb] && !Bits[ARM::HasV8Ops]);
16585 return (!Bits[ARM::ModeThumb] && Bits[ARM::HasV8Ops]);
16587 return (!Bits[ARM::ModeThumb] && Bits[ARM::HasV8Ops] && Bits[ARM::HasV8_1aOps]);
16633 return (Bits[ARM::HasV8Ops] && Bits[ARM::FeatureCrypto]);
16653 return (Bits[ARM::ModeThumb] && Bits[ARM::FeatureThumb2] && Bits[ARM::HasV8Ops] && Bits[ARM::HasV8_1aOps]);
16657 return (Bits[ARM::ModeThumb] && Bits[ARM::HasV8Ops]);
16681 return (Bits[ARM::ModeThumb] && Bits[ARM::FeatureThumb2] && Bits[ARM::HasV8Ops]);
16707 return (Bits[ARM::ModeThumb] && Bits[ARM::FeatureThumb2] && Bits[ARM::HasV8Ops] && Bits[ARM::FeatureCRC]);
16709 return (Bits[ARM::ModeThumb] && Bits[ARM::FeatureThumb2] && !Bits[ARM::HasV8Ops]);
16711 return (!Bits[ARM::HasV8Ops] && Bits[ARM::ModeThumb] && Bits[ARM::FeatureThumb2]);
16751 return (Bits[ARM::HasV8Ops] && Bits[ARM::FeatureNEON] && Bits[ARM::FeatureFullFP16]);
16753 return (Bits[ARM::HasV8Ops] && Bits[ARM::FeatureNEON]);
gen/lib/Target/ARM/ARMGenInstrInfo.inc 7523 { 1690, 1, 0, 4, 841, 0|(1ULL<<MCID::UnmodeledSideEffects), 0xd00ULL, nullptr, nullptr, OperandInfo2, ARM::HasV8Ops ,nullptr }, // Inst #1690 = SETEND
10024 { 4191, 1, 0, 2, 841, 0|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo2, ARM::HasV8Ops ,nullptr }, // Inst #4191 = tSETEND
gen/lib/Target/ARM/ARMGenSubtargetInfo.inc 354 { "v8", "Support ARM v8 instructions", ARM::HasV8Ops, { { { 0x1000000000ULL, 0x0ULL, 0x80ULL, } } } },
19519 if (Bits[ARM::HasV8Ops]) HasV8Ops = true;
lib/Target/ARM/ARMBaseInstrInfo.h 537 if (featureBits[ARM::HasV8Ops] && (Num & 0xE) != 0xE)
lib/Target/ARM/AsmParser/ARMAsmParser.cpp 485 return getSTI().getFeatureBits()[ARM::HasV8Ops];
lib/Target/ARM/Disassembler/ARMDisassembler.cpp 1271 if ((RegNo == 13 && !featureBits[ARM::HasV8Ops]) || RegNo == 15)
1715 if (featureBits[ARM::HasV8Ops] && (coproc != 14))
2517 !FeatureBits[ARM::HasV8Ops])
5883 if (featureBits[ARM::ModeThumb] && !featureBits[ARM::HasV8Ops]) {
lib/Target/ARM/MCTargetDesc/ARMInstPrinter.cpp 753 O << ARM_MB::MemBOptToString(val, STI.getFeatureBits()[ARM::HasV8Ops]);
lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp 71 if (STI.getFeatureBits()[llvm::ARM::HasV8Ops] && MI.getOperand(1).isImm() &&
lib/Target/ARM/MCTargetDesc/ARMTargetStreamer.cpp 123 if (STI.hasFeature(ARM::HasV8Ops)) {
221 if (STI.hasFeature(ARM::HasV8Ops))
278 if (STI.hasFeature(ARM::FeatureHWDivARM) && !STI.hasFeature(ARM::HasV8Ops))