|
|
reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
|
References
gen/lib/Target/ARM/ARMGenInstrInfo.inc 5392 static const MCOperandInfo OperandInfo80[] = { { ARM::tcGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
5482 static const MCOperandInfo OperandInfo170[] = { { ARM::tcGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::tcGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::OptionalDef), MCOI::OPERAND_UNKNOWN, 0 }, };
5482 static const MCOperandInfo OperandInfo170[] = { { ARM::tcGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::tcGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::OptionalDef), MCOI::OPERAND_UNKNOWN, 0 }, };
gen/lib/Target/ARM/ARMGenRegisterBank.inc 77 (1u << (ARM::tcGPRRegClassID - 0)) |
gen/lib/Target/ARM/ARMGenRegisterInfo.inc 2911 { tcGPR, tcGPRBits, 1308, 5, sizeof(tcGPRBits), ARM::tcGPRRegClassID, 1, true },
6086 const MCRegisterClass &MCR = ARMMCRegisterClasses[ARM::tcGPRRegClassID];
6786 &ARMMCRegisterClasses[tcGPRRegClassID],
lib/Target/ARM/ARMRegisterBankInfo.cpp 159 assert(RBGPR.covers(*TRI.getRegClass(ARM::tcGPRRegClassID)) &&
186 case tcGPRRegClassID: