reference, declarationdefinition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced

References

gen/lib/Target/ARM/ARMGenRegisterInfo.inc
 8440     { ARM::dsub_0, ARM::dsub_1, ARM::dsub_2, ARM::dsub_3, ARM::dsub_4, 0, ARM::dsub_6, 0, 0, 0, 0, 0, ARM::qsub_0, ARM::qsub_1, 0, 0, ARM::ssub_0, ARM::ssub_1, ARM::ssub_2, ARM::ssub_3, ARM::ssub_4, ARM::ssub_5, ARM::ssub_6, ARM::ssub_7, ARM::ssub_8, ARM::ssub_9, 0, 0, ARM::ssub_12, ARM::ssub_13, 0, 0, ARM::ssub_0_ssub_1_ssub_4_ssub_5, ARM::ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5, ARM::ssub_2_ssub_3_ssub_6_ssub_7, ARM::ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7, ARM::ssub_2_ssub_3_ssub_4_ssub_5, ARM::ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9, 0, 0, 0, 0, ARM::ssub_4_ssub_5_ssub_8_ssub_9, 0, ARM::ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13, 0, 0, 0, 0, 0, ARM::ssub_8_ssub_9_ssub_12_ssub_13, 0, 0, 0, 0, 0, },
 8441     { ARM::dsub_1, ARM::dsub_2, ARM::dsub_3, ARM::dsub_4, ARM::dsub_5, 0, ARM::dsub_7, 0, 0, 0, 0, 0, ARM::ssub_2_ssub_3_ssub_4_ssub_5, ARM::ssub_6_ssub_7_ssub_8_ssub_9, 0, 0, ARM::ssub_2, ARM::ssub_3, ARM::ssub_4, ARM::ssub_5, ARM::ssub_6, ARM::ssub_7, ARM::ssub_8, ARM::ssub_9, ARM::ssub_10, ARM::ssub_11, 0, 0, ARM::dsub_7_then_ssub_0, ARM::dsub_7_then_ssub_1, 0, 0, ARM::ssub_2_ssub_3_ssub_6_ssub_7, ARM::ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7, ARM::ssub_4_ssub_5_ssub_8_ssub_9, ARM::ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9, ARM::qsub_1, ARM::ssub_2_ssub_3_ssub_6_ssub_7_dsub_5, 0, 0, 0, 0, ARM::ssub_6_ssub_7_dsub_5, 0, ARM::ssub_6_ssub_7_dsub_5_dsub_7, 0, 0, 0, 0, 0, ARM::dsub_5_dsub_7, 0, 0, 0, 0, 0, },
 8442     { ARM::dsub_2, ARM::dsub_3, ARM::dsub_4, ARM::dsub_5, ARM::dsub_6, 0, 0, 0, 0, 0, 0, 0, ARM::qsub_1, ARM::qsub_2, 0, 0, ARM::ssub_4, ARM::ssub_5, ARM::ssub_6, ARM::ssub_7, ARM::ssub_8, ARM::ssub_9, ARM::ssub_10, ARM::ssub_11, ARM::ssub_12, ARM::ssub_13, 0, 0, 0, 0, 0, 0, ARM::ssub_4_ssub_5_ssub_8_ssub_9, ARM::ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9, ARM::ssub_6_ssub_7_dsub_5, ARM::ssub_6_ssub_7_ssub_8_ssub_9_dsub_5, ARM::ssub_6_ssub_7_ssub_8_ssub_9, 0, 0, 0, 0, 0, ARM::ssub_8_ssub_9_ssub_12_ssub_13, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, },
 8443     { ARM::dsub_3, ARM::dsub_4, ARM::dsub_5, ARM::dsub_6, ARM::dsub_7, 0, 0, 0, 0, 0, 0, 0, ARM::ssub_6_ssub_7_ssub_8_ssub_9, ARM::dsub_5_ssub_12_ssub_13, 0, 0, ARM::ssub_6, ARM::ssub_7, ARM::ssub_8, ARM::ssub_9, ARM::ssub_10, ARM::ssub_11, ARM::ssub_12, ARM::ssub_13, ARM::dsub_7_then_ssub_0, ARM::dsub_7_then_ssub_1, 0, 0, 0, 0, 0, 0, ARM::ssub_6_ssub_7_dsub_5, ARM::ssub_6_ssub_7_ssub_8_ssub_9_dsub_5, ARM::ssub_8_ssub_9_ssub_12_ssub_13, ARM::ssub_8_ssub_9_dsub_5_ssub_12_ssub_13, ARM::qsub_2, 0, 0, 0, 0, 0, ARM::dsub_5_dsub_7, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, },