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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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References
gen/lib/Target/ARM/ARMGenRegisterInfo.inc 3826 { 16, 16, 32, VTLists+2 }, // HPR
3827 { 32, 32, 32, VTLists+4 }, // FPWithVPR
3828 { 32, 32, 32, VTLists+4 }, // SPR
3829 { 32, 32, 32, VTLists+4 }, // FPWithVPR_with_ssub_0
3830 { 32, 32, 32, VTLists+0 }, // GPR
3831 { 32, 32, 32, VTLists+0 }, // GPRwithAPSR
3832 { 32, 32, 32, VTLists+0 }, // GPRwithZR
3833 { 32, 32, 32, VTLists+4 }, // SPR_8
3834 { 32, 32, 32, VTLists+0 }, // GPRnopc
3835 { 32, 32, 32, VTLists+0 }, // GPRwithAPSRnosp
3836 { 32, 32, 32, VTLists+0 }, // GPRwithZRnosp
3837 { 32, 32, 32, VTLists+0 }, // rGPR
3838 { 32, 32, 32, VTLists+0 }, // tGPRwithpc
3839 { 32, 32, 32, VTLists+4 }, // FPWithVPR_with_ssub_0_with_ssub_0_in_SPR_8
3840 { 32, 32, 32, VTLists+0 }, // hGPR
3841 { 32, 32, 32, VTLists+0 }, // tGPR
3842 { 32, 32, 32, VTLists+0 }, // tGPREven
3843 { 32, 32, 32, VTLists+0 }, // GPRnopc_and_hGPR
3844 { 32, 32, 32, VTLists+0 }, // GPRwithAPSRnosp_and_hGPR
3845 { 32, 32, 32, VTLists+0 }, // tGPROdd
3846 { 32, 32, 32, VTLists+0 }, // tcGPR
3847 { 32, 32, 32, VTLists+0 }, // hGPR_and_tGPREven
3848 { 32, 32, 32, VTLists+0 }, // tGPR_and_tGPREven
3849 { 32, 32, 32, VTLists+0 }, // tGPR_and_tGPROdd
3850 { 32, 32, 32, VTLists+0 }, // tGPR_and_tcGPR
3851 { 32, 32, 32, VTLists+0 }, // tGPREven_and_tcGPR
3852 { 32, 32, 32, VTLists+0 }, // hGPR_and_tGPROdd
3853 { 32, 32, 32, VTLists+0 }, // tGPREven_and_tGPR_and_tcGPR
3854 { 32, 32, 32, VTLists+0 }, // tGPROdd_and_tcGPR
3855 { 32, 32, 32, VTLists+0 }, // CCR
3856 { 32, 32, 32, VTLists+0 }, // GPRlr
3857 { 32, 32, 32, VTLists+0 }, // GPRsp
3858 { 32, 32, 32, VTLists+6 }, // VCCR
3859 { 32, 32, 32, VTLists+0 }, // cl_FPSCR_NZCV
3860 { 32, 32, 32, VTLists+0 }, // hGPR_and_tGPRwithpc
3861 { 32, 32, 32, VTLists+0 }, // hGPR_and_tcGPR
3862 { 64, 64, 64, VTLists+17 }, // DPR
3863 { 64, 64, 64, VTLists+17 }, // DPR_VFP2
3864 { 64, 64, 64, VTLists+17 }, // DPR_8
3865 { 64, 64, 64, VTLists+40 }, // GPRPair
3866 { 64, 64, 64, VTLists+40 }, // GPRPairnosp
3867 { 64, 64, 64, VTLists+40 }, // GPRPair_with_gsub_0_in_tGPR
3868 { 64, 64, 64, VTLists+40 }, // GPRPair_with_gsub_0_in_hGPR
3869 { 64, 64, 64, VTLists+40 }, // GPRPair_with_gsub_0_in_tcGPR
3870 { 64, 64, 64, VTLists+40 }, // GPRPair_with_gsub_1_in_tcGPR
3871 { 64, 64, 64, VTLists+40 }, // GPRPairnosp_and_GPRPair_with_gsub_0_in_hGPR
3872 { 64, 64, 64, VTLists+40 }, // GPRPair_with_gsub_1_in_GPRsp
3873 { 128, 128, 64, VTLists+11 }, // DPairSpc
3874 { 128, 128, 64, VTLists+11 }, // DPairSpc_with_ssub_0
3875 { 128, 128, 64, VTLists+11 }, // DPairSpc_with_ssub_4
3876 { 128, 128, 64, VTLists+11 }, // DPairSpc_with_dsub_0_in_DPR_8
3877 { 128, 128, 64, VTLists+11 }, // DPairSpc_with_dsub_2_in_DPR_8
3878 { 128, 128, 128, VTLists+33 }, // DPair
3879 { 128, 128, 128, VTLists+33 }, // DPair_with_ssub_0
3880 { 128, 128, 128, VTLists+25 }, // QPR
3881 { 128, 128, 128, VTLists+33 }, // DPair_with_ssub_2
3882 { 128, 128, 128, VTLists+33 }, // DPair_with_dsub_0_in_DPR_8
3883 { 128, 128, 128, VTLists+25 }, // MQPR
3884 { 128, 128, 128, VTLists+33 }, // QPR_VFP2
3885 { 128, 128, 128, VTLists+33 }, // DPair_with_dsub_1_in_DPR_8
3886 { 128, 128, 128, VTLists+33 }, // QPR_8
3887 { 192, 192, 64, VTLists+40 }, // DTriple
3888 { 192, 192, 64, VTLists+40 }, // DTripleSpc
3889 { 192, 192, 64, VTLists+40 }, // DTripleSpc_with_ssub_0
3890 { 192, 192, 64, VTLists+40 }, // DTriple_with_ssub_0
3891 { 192, 192, 64, VTLists+40 }, // DTriple_with_qsub_0_in_QPR
3892 { 192, 192, 64, VTLists+40 }, // DTriple_with_ssub_2
3893 { 192, 192, 64, VTLists+40 }, // DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR
3894 { 192, 192, 64, VTLists+40 }, // DTripleSpc_with_ssub_4
3895 { 192, 192, 64, VTLists+40 }, // DTriple_with_ssub_4
3896 { 192, 192, 64, VTLists+40 }, // DTripleSpc_with_ssub_8
3897 { 192, 192, 64, VTLists+40 }, // DTripleSpc_with_dsub_0_in_DPR_8
3898 { 192, 192, 64, VTLists+40 }, // DTriple_with_dsub_0_in_DPR_8
3899 { 192, 192, 64, VTLists+40 }, // DTriple_with_qsub_0_in_MQPR
3900 { 192, 192, 64, VTLists+40 }, // DTriple_with_ssub_0_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR
3901 { 192, 192, 64, VTLists+40 }, // DTriple_with_dsub_1_in_DPR_8
3902 { 192, 192, 64, VTLists+40 }, // DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPR
3903 { 192, 192, 64, VTLists+40 }, // DTriple_with_ssub_4_and_DTriple_with_qsub_0_in_MQPR
3904 { 192, 192, 64, VTLists+40 }, // DTripleSpc_with_dsub_2_in_DPR_8
3905 { 192, 192, 64, VTLists+40 }, // DTriple_with_dsub_2_in_DPR_8
3906 { 192, 192, 64, VTLists+40 }, // DTripleSpc_with_dsub_4_in_DPR_8
3907 { 192, 192, 64, VTLists+40 }, // DTriple_with_dsub_0_in_DPR_8_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPR
3908 { 192, 192, 64, VTLists+40 }, // DTriple_with_qsub_0_in_QPR_8
3909 { 192, 192, 64, VTLists+40 }, // DTriple_with_dsub_2_in_DPR_8_and_DTriple_with_qsub_0_in_MQPR
3910 { 192, 192, 64, VTLists+40 }, // DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8
3911 { 256, 256, 64, VTLists+13 }, // DQuadSpc
3912 { 256, 256, 64, VTLists+13 }, // DQuadSpc_with_ssub_0
3913 { 256, 256, 64, VTLists+13 }, // DQuadSpc_with_ssub_4
3914 { 256, 256, 64, VTLists+13 }, // DQuadSpc_with_ssub_8
3915 { 256, 256, 64, VTLists+13 }, // DQuadSpc_with_dsub_0_in_DPR_8
3916 { 256, 256, 64, VTLists+13 }, // DQuadSpc_with_dsub_2_in_DPR_8
3917 { 256, 256, 64, VTLists+13 }, // DQuadSpc_with_dsub_4_in_DPR_8
3918 { 256, 256, 256, VTLists+13 }, // DQuad
3919 { 256, 256, 256, VTLists+13 }, // DQuad_with_ssub_0
3920 { 256, 256, 256, VTLists+13 }, // DQuad_with_ssub_2
3921 { 256, 256, 256, VTLists+13 }, // QQPR
3922 { 256, 256, 256, VTLists+13 }, // DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR
3923 { 256, 256, 256, VTLists+13 }, // DQuad_with_ssub_4
3924 { 256, 256, 256, VTLists+13 }, // DQuad_with_ssub_6
3925 { 256, 256, 256, VTLists+13 }, // DQuad_with_dsub_0_in_DPR_8
3926 { 256, 256, 256, VTLists+13 }, // DQuad_with_qsub_0_in_MQPR
3927 { 256, 256, 256, VTLists+13 }, // DQuad_with_ssub_0_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR
3928 { 256, 256, 256, VTLists+13 }, // DQuad_with_dsub_1_in_DPR_8
3929 { 256, 256, 256, VTLists+13 }, // DQuad_with_qsub_1_in_MQPR
3930 { 256, 256, 256, VTLists+13 }, // DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPR
3931 { 256, 256, 256, VTLists+13 }, // DQuad_with_dsub_2_in_DPR_8
3932 { 256, 256, 256, VTLists+13 }, // DQuad_with_ssub_6_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPR
3933 { 256, 256, 256, VTLists+13 }, // DQuad_with_dsub_3_in_DPR_8
3934 { 256, 256, 256, VTLists+13 }, // DQuad_with_dsub_0_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPR
3935 { 256, 256, 256, VTLists+13 }, // DQuad_with_qsub_0_in_QPR_8
3936 { 256, 256, 256, VTLists+13 }, // DQuad_with_qsub_1_in_QPR_8
3937 { 256, 256, 256, VTLists+13 }, // DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8
3938 { 256, 256, 256, VTLists+13 }, // DQuad_with_dsub_3_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPR
3939 { 512, 512, 256, VTLists+15 }, // QQQQPR
3940 { 512, 512, 256, VTLists+15 }, // QQQQPR_with_ssub_0
3941 { 512, 512, 256, VTLists+15 }, // QQQQPR_with_ssub_4
3942 { 512, 512, 256, VTLists+15 }, // QQQQPR_with_ssub_8
3943 { 512, 512, 256, VTLists+15 }, // QQQQPR_with_ssub_12
3944 { 512, 512, 256, VTLists+15 }, // QQQQPR_with_dsub_0_in_DPR_8
3945 { 512, 512, 256, VTLists+15 }, // QQQQPR_with_dsub_2_in_DPR_8
3946 { 512, 512, 256, VTLists+15 }, // QQQQPR_with_dsub_4_in_DPR_8
3947 { 512, 512, 256, VTLists+15 }, // QQQQPR_with_dsub_6_in_DPR_8