|
|
reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
|
References
gen/lib/Target/ARM/ARMGenAsmMatcher.inc 7859 DiagnosticPredicate DP(Operand.isMemImm7ShiftedOffset<0,ARM::GPRnopcRegClassID>());
7873 DiagnosticPredicate DP(Operand.isMemImm7ShiftedOffset<1,ARM::GPRnopcRegClassID>());
7887 DiagnosticPredicate DP(Operand.isMemImm7ShiftedOffset<2,ARM::GPRnopcRegClassID>());
gen/lib/Target/ARM/ARMGenGlobalISel.inc 895 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
919 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
991 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
1015 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
1087 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
1096 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/ARM::GPRnopcRegClassID,
1102 GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/ARM::GPRnopcRegClassID,
1159 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
1169 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/ARM::GPRnopcRegClassID,
1175 GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/ARM::GPRnopcRegClassID,
1254 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
1255 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::GPRnopcRegClassID,
1277 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
1299 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
1304 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::GPRnopcRegClassID,
1305 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::GPRnopcRegClassID,
1306 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRnopcRegClassID,
1324 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
1329 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::GPRnopcRegClassID,
1330 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::GPRnopcRegClassID,
1331 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRnopcRegClassID,
1421 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
1422 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::GPRnopcRegClassID,
1427 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::GPRnopcRegClassID,
1428 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::GPRnopcRegClassID,
1446 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
1447 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::GPRnopcRegClassID,
1452 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::GPRnopcRegClassID,
1453 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::GPRnopcRegClassID,
1561 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
1562 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::GPRnopcRegClassID,
1579 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
1581 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRnopcRegClassID,
3584 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
3585 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::GPRnopcRegClassID,
3607 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
3695 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
3696 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::GPRnopcRegClassID,
4451 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
4452 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::GPRnopcRegClassID,
4453 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRnopcRegClassID,
4469 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
4470 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::GPRnopcRegClassID,
4471 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRnopcRegClassID,
4806 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
4852 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
4869 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
4886 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
5872 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
5881 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/ARM::GPRnopcRegClassID,
5892 GIM_CheckRegBankForClass, /*MI*/4, /*Op*/1, /*RC*/ARM::GPRnopcRegClassID,
5954 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
5963 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/ARM::GPRnopcRegClassID,
5974 GIM_CheckRegBankForClass, /*MI*/4, /*Op*/1, /*RC*/ARM::GPRnopcRegClassID,
6036 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
6045 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/ARM::GPRnopcRegClassID,
6056 GIM_CheckRegBankForClass, /*MI*/4, /*Op*/1, /*RC*/ARM::GPRnopcRegClassID,
6118 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
6123 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::GPRnopcRegClassID,
6133 GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/ARM::GPRnopcRegClassID,
6200 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
6205 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::GPRnopcRegClassID,
6215 GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/ARM::GPRnopcRegClassID,
6282 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
6287 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::GPRnopcRegClassID,
6297 GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/ARM::GPRnopcRegClassID,
6364 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
6369 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::GPRnopcRegClassID,
6375 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/ARM::GPRnopcRegClassID,
6424 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
6429 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::GPRnopcRegClassID,
6435 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/ARM::GPRnopcRegClassID,
6484 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
6489 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::GPRnopcRegClassID,
6495 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/ARM::GPRnopcRegClassID,
6554 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
6559 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::GPRnopcRegClassID,
6565 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/ARM::GPRnopcRegClassID,
6624 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
6629 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::GPRnopcRegClassID,
6635 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/ARM::GPRnopcRegClassID,
6694 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
6699 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::GPRnopcRegClassID,
6709 GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/ARM::GPRnopcRegClassID,
6764 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
6769 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::GPRnopcRegClassID,
6779 GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/ARM::GPRnopcRegClassID,
6834 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
6839 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::GPRnopcRegClassID,
6849 GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/ARM::GPRnopcRegClassID,
7068 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
11710 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
13750 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
14049 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
14055 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::GPRnopcRegClassID,
14058 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::GPRnopcRegClassID,
14467 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
14468 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRnopcRegClassID,
14474 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::GPRnopcRegClassID,
14525 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
14526 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRnopcRegClassID,
14532 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::GPRnopcRegClassID,
14583 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
14584 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRnopcRegClassID,
14610 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
14611 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRnopcRegClassID,
15089 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
15090 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRnopcRegClassID,
15091 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::GPRnopcRegClassID,
15110 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
15111 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRnopcRegClassID,
15112 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::GPRnopcRegClassID,
15131 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
15132 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRnopcRegClassID,
15133 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::GPRnopcRegClassID,
15152 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
15153 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRnopcRegClassID,
15154 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::GPRnopcRegClassID,
15173 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
15174 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRnopcRegClassID,
15175 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::GPRnopcRegClassID,
15194 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
15195 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRnopcRegClassID,
15196 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::GPRnopcRegClassID,
15215 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
15216 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRnopcRegClassID,
15217 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::GPRnopcRegClassID,
15236 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
15237 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRnopcRegClassID,
15238 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::GPRnopcRegClassID,
15257 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
15258 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRnopcRegClassID,
15259 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::GPRnopcRegClassID,
15278 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
15279 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRnopcRegClassID,
15280 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::GPRnopcRegClassID,
15299 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
15300 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRnopcRegClassID,
15301 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::GPRnopcRegClassID,
15320 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
15321 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRnopcRegClassID,
15322 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::GPRnopcRegClassID,
15341 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
15342 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRnopcRegClassID,
15343 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::GPRnopcRegClassID,
15362 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
15363 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRnopcRegClassID,
15364 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::GPRnopcRegClassID,
15383 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
15384 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRnopcRegClassID,
15385 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::GPRnopcRegClassID,
15404 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
15405 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRnopcRegClassID,
15406 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::GPRnopcRegClassID,
15425 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
15426 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRnopcRegClassID,
15427 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::GPRnopcRegClassID,
15446 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
15447 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRnopcRegClassID,
15448 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::GPRnopcRegClassID,
15467 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
15468 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRnopcRegClassID,
15469 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::GPRnopcRegClassID,
15488 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
15489 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRnopcRegClassID,
15490 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::GPRnopcRegClassID,
15509 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
15510 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRnopcRegClassID,
15511 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::GPRnopcRegClassID,
15530 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
15531 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRnopcRegClassID,
15532 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::GPRnopcRegClassID,
15551 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
15552 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRnopcRegClassID,
15553 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::GPRnopcRegClassID,
15572 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
15573 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRnopcRegClassID,
15574 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::GPRnopcRegClassID,
15593 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
15594 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRnopcRegClassID,
15595 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::GPRnopcRegClassID,
15614 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
15615 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRnopcRegClassID,
15616 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::GPRnopcRegClassID,
15656 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
15657 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRnopcRegClassID,
15658 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::GPRnopcRegClassID,
15675 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
15676 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRnopcRegClassID,
15677 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::GPRnopcRegClassID,
15694 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
15695 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRnopcRegClassID,
15696 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::GPRnopcRegClassID,
15713 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
15714 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRnopcRegClassID,
15715 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::GPRnopcRegClassID,
15732 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
15733 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRnopcRegClassID,
15734 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::GPRnopcRegClassID,
15751 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
15752 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRnopcRegClassID,
15753 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::GPRnopcRegClassID,
21376 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
21398 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
21420 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
21421 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRnopcRegClassID,
21422 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::GPRnopcRegClassID,
21441 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
21442 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRnopcRegClassID,
21443 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::GPRnopcRegClassID,
21462 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
21463 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRnopcRegClassID,
21464 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::GPRnopcRegClassID,
21483 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
21484 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRnopcRegClassID,
21485 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::GPRnopcRegClassID,
22215 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
22216 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRnopcRegClassID,
22217 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::GPRnopcRegClassID,
22239 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
22240 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRnopcRegClassID,
22241 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::GPRnopcRegClassID,
22263 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
22264 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRnopcRegClassID,
22265 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::GPRnopcRegClassID,
22287 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
22288 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRnopcRegClassID,
22289 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::GPRnopcRegClassID,
22311 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
22335 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
22359 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
22383 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
22407 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
22431 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
23444 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
23474 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::GPRnopcRegClassID,
23537 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
23538 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRnopcRegClassID,
23539 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::GPRnopcRegClassID,
23559 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
23560 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRnopcRegClassID,
23561 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::GPRnopcRegClassID,
23581 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
23582 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRnopcRegClassID,
23583 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::GPRnopcRegClassID,
23603 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
23604 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRnopcRegClassID,
23605 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::GPRnopcRegClassID,
23625 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
23626 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRnopcRegClassID,
23627 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::GPRnopcRegClassID,
23647 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
23648 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRnopcRegClassID,
23649 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::GPRnopcRegClassID,
23669 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
23670 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRnopcRegClassID,
23671 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::GPRnopcRegClassID,
23691 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
23692 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRnopcRegClassID,
23693 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::GPRnopcRegClassID,
23713 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
23714 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRnopcRegClassID,
23715 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::GPRnopcRegClassID,
23735 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
23736 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRnopcRegClassID,
23737 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::GPRnopcRegClassID,
23757 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
23758 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRnopcRegClassID,
23759 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::GPRnopcRegClassID,
23779 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
23780 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRnopcRegClassID,
23781 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::GPRnopcRegClassID,
24094 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::GPRnopcRegClassID,
24095 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/ARM::GPRnopcRegClassID,
24122 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::GPRnopcRegClassID,
24123 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/ARM::GPRnopcRegClassID,
gen/lib/Target/ARM/ARMGenInstrInfo.inc 5352 static const MCOperandInfo OperandInfo40[] = { { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
5352 static const MCOperandInfo OperandInfo40[] = { { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
5355 static const MCOperandInfo OperandInfo43[] = { { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::OptionalDef), MCOI::OPERAND_UNKNOWN, 0 }, };
5355 static const MCOperandInfo OperandInfo43[] = { { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::OptionalDef), MCOI::OPERAND_UNKNOWN, 0 }, };
5355 static const MCOperandInfo OperandInfo43[] = { { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::OptionalDef), MCOI::OPERAND_UNKNOWN, 0 }, };
5363 static const MCOperandInfo OperandInfo51[] = { { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
5373 static const MCOperandInfo OperandInfo61[] = { { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, (1 << MCOI::EARLY_CLOBBER) }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::OptionalDef), MCOI::OPERAND_UNKNOWN, 0 }, };
5373 static const MCOperandInfo OperandInfo61[] = { { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, (1 << MCOI::EARLY_CLOBBER) }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::OptionalDef), MCOI::OPERAND_UNKNOWN, 0 }, };
5373 static const MCOperandInfo OperandInfo61[] = { { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, (1 << MCOI::EARLY_CLOBBER) }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::OptionalDef), MCOI::OPERAND_UNKNOWN, 0 }, };
5373 static const MCOperandInfo OperandInfo61[] = { { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, (1 << MCOI::EARLY_CLOBBER) }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::OptionalDef), MCOI::OPERAND_UNKNOWN, 0 }, };
5378 static const MCOperandInfo OperandInfo66[] = { { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
5378 static const MCOperandInfo OperandInfo66[] = { { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
5382 static const MCOperandInfo OperandInfo70[] = { { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, (1 << MCOI::EARLY_CLOBBER) }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::OptionalDef), MCOI::OPERAND_UNKNOWN, 0 }, };
5382 static const MCOperandInfo OperandInfo70[] = { { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, (1 << MCOI::EARLY_CLOBBER) }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::OptionalDef), MCOI::OPERAND_UNKNOWN, 0 }, };
5382 static const MCOperandInfo OperandInfo70[] = { { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, (1 << MCOI::EARLY_CLOBBER) }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::OptionalDef), MCOI::OPERAND_UNKNOWN, 0 }, };
5389 static const MCOperandInfo OperandInfo77[] = { { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, (1 << MCOI::EARLY_CLOBBER) }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
5402 static const MCOperandInfo OperandInfo90[] = { { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
5403 static const MCOperandInfo OperandInfo91[] = { { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
5404 static const MCOperandInfo OperandInfo92[] = { { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
5406 static const MCOperandInfo OperandInfo94[] = { { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
5415 static const MCOperandInfo OperandInfo103[] = { { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
5415 static const MCOperandInfo OperandInfo103[] = { { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
5420 static const MCOperandInfo OperandInfo108[] = { { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, (1 << MCOI::EARLY_CLOBBER) }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
5420 static const MCOperandInfo OperandInfo108[] = { { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, (1 << MCOI::EARLY_CLOBBER) }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
5442 static const MCOperandInfo OperandInfo130[] = { { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::OptionalDef), MCOI::OPERAND_UNKNOWN, 0 }, };
5442 static const MCOperandInfo OperandInfo130[] = { { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::OptionalDef), MCOI::OPERAND_UNKNOWN, 0 }, };
5442 static const MCOperandInfo OperandInfo130[] = { { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::OptionalDef), MCOI::OPERAND_UNKNOWN, 0 }, };
5442 static const MCOperandInfo OperandInfo130[] = { { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::OptionalDef), MCOI::OPERAND_UNKNOWN, 0 }, };
5443 static const MCOperandInfo OperandInfo131[] = { { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::OptionalDef), MCOI::OPERAND_UNKNOWN, 0 }, };
5443 static const MCOperandInfo OperandInfo131[] = { { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::OptionalDef), MCOI::OPERAND_UNKNOWN, 0 }, };
5446 static const MCOperandInfo OperandInfo134[] = { { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
5446 static const MCOperandInfo OperandInfo134[] = { { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
5451 static const MCOperandInfo OperandInfo139[] = { { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
5451 static const MCOperandInfo OperandInfo139[] = { { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
5451 static const MCOperandInfo OperandInfo139[] = { { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
5453 static const MCOperandInfo OperandInfo141[] = { { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
5453 static const MCOperandInfo OperandInfo141[] = { { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
5453 static const MCOperandInfo OperandInfo141[] = { { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
5464 static const MCOperandInfo OperandInfo152[] = { { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, ((1 << 16) | (1 << MCOI::TIED_TO)) }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
5466 static const MCOperandInfo OperandInfo154[] = { { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
5467 static const MCOperandInfo OperandInfo155[] = { { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
5467 static const MCOperandInfo OperandInfo155[] = { { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
5471 static const MCOperandInfo OperandInfo159[] = { { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, ((1 << 16) | (1 << MCOI::TIED_TO)) }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
5471 static const MCOperandInfo OperandInfo159[] = { { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, ((1 << 16) | (1 << MCOI::TIED_TO)) }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
5471 static const MCOperandInfo OperandInfo159[] = { { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, ((1 << 16) | (1 << MCOI::TIED_TO)) }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
5473 static const MCOperandInfo OperandInfo161[] = { { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
5476 static const MCOperandInfo OperandInfo164[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
5476 static const MCOperandInfo OperandInfo164[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
5477 static const MCOperandInfo OperandInfo165[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
5477 static const MCOperandInfo OperandInfo165[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
5478 static const MCOperandInfo OperandInfo166[] = { { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::OptionalDef), MCOI::OPERAND_UNKNOWN, 0 }, };
5478 static const MCOperandInfo OperandInfo166[] = { { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::OptionalDef), MCOI::OPERAND_UNKNOWN, 0 }, };
5478 static const MCOperandInfo OperandInfo166[] = { { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::OptionalDef), MCOI::OPERAND_UNKNOWN, 0 }, };
5478 static const MCOperandInfo OperandInfo166[] = { { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::OptionalDef), MCOI::OPERAND_UNKNOWN, 0 }, };
5480 static const MCOperandInfo OperandInfo168[] = { { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
5484 static const MCOperandInfo OperandInfo172[] = { { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::OptionalDef), MCOI::OPERAND_UNKNOWN, 0 }, };
5487 static const MCOperandInfo OperandInfo175[] = { { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
5487 static const MCOperandInfo OperandInfo175[] = { { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
5488 static const MCOperandInfo OperandInfo176[] = { { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
5488 static const MCOperandInfo OperandInfo176[] = { { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
5489 static const MCOperandInfo OperandInfo177[] = { { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
5491 static const MCOperandInfo OperandInfo179[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
5522 static const MCOperandInfo OperandInfo210[] = { { ARM::QQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::QQPRRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, };
5524 static const MCOperandInfo OperandInfo212[] = { { ARM::QQQQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::QQQQPRRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, };
5528 static const MCOperandInfo OperandInfo216[] = { { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, (1 << MCOI::EARLY_CLOBBER) }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, ARM::OPERAND_VPRED_N, 0 }, { ARM::VCCRRegClassID, 0, ARM::OPERAND_VPRED_N, 0 }, };
5529 static const MCOperandInfo OperandInfo217[] = { { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, ARM::OPERAND_VPRED_N, 0 }, { ARM::VCCRRegClassID, 0, ARM::OPERAND_VPRED_N, 0 }, };
5530 static const MCOperandInfo OperandInfo218[] = { { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_MEMORY, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, ARM::OPERAND_VPRED_N, 0 }, { ARM::VCCRRegClassID, 0, ARM::OPERAND_VPRED_N, 0 }, };
5555 static const MCOperandInfo OperandInfo243[] = { { ARM::QQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, };
5557 static const MCOperandInfo OperandInfo245[] = { { ARM::QQQQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, };
5559 static const MCOperandInfo OperandInfo247[] = { { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, ARM::OPERAND_VPRED_N, 0 }, { ARM::VCCRRegClassID, 0, ARM::OPERAND_VPRED_N, 0 }, };
5563 static const MCOperandInfo OperandInfo251[] = { { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::OptionalDef), MCOI::OPERAND_UNKNOWN, 0 }, };
5563 static const MCOperandInfo OperandInfo251[] = { { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::OptionalDef), MCOI::OPERAND_UNKNOWN, 0 }, };
5563 static const MCOperandInfo OperandInfo251[] = { { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::OptionalDef), MCOI::OPERAND_UNKNOWN, 0 }, };
5566 static const MCOperandInfo OperandInfo254[] = { { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
5566 static const MCOperandInfo OperandInfo254[] = { { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
5566 static const MCOperandInfo OperandInfo254[] = { { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
5568 static const MCOperandInfo OperandInfo256[] = { { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, };
5569 static const MCOperandInfo OperandInfo257[] = { { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
5569 static const MCOperandInfo OperandInfo257[] = { { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
5569 static const MCOperandInfo OperandInfo257[] = { { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
5570 static const MCOperandInfo OperandInfo258[] = { { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
5570 static const MCOperandInfo OperandInfo258[] = { { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
5572 static const MCOperandInfo OperandInfo260[] = { { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
5572 static const MCOperandInfo OperandInfo260[] = { { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
5572 static const MCOperandInfo OperandInfo260[] = { { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
5574 static const MCOperandInfo OperandInfo262[] = { { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, ((1 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
5574 static const MCOperandInfo OperandInfo262[] = { { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, ((1 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
5574 static const MCOperandInfo OperandInfo262[] = { { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, ((1 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
5574 static const MCOperandInfo OperandInfo262[] = { { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, ((1 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
5574 static const MCOperandInfo OperandInfo262[] = { { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, ((1 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
5574 static const MCOperandInfo OperandInfo262[] = { { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, ((1 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
5576 static const MCOperandInfo OperandInfo264[] = { { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
5576 static const MCOperandInfo OperandInfo264[] = { { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
5577 static const MCOperandInfo OperandInfo265[] = { { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
5577 static const MCOperandInfo OperandInfo265[] = { { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
5580 static const MCOperandInfo OperandInfo268[] = { { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
5581 static const MCOperandInfo OperandInfo269[] = { { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, (1 << MCOI::EARLY_CLOBBER) }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
5586 static const MCOperandInfo OperandInfo274[] = { { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
5586 static const MCOperandInfo OperandInfo274[] = { { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
5587 static const MCOperandInfo OperandInfo275[] = { { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
5587 static const MCOperandInfo OperandInfo275[] = { { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
5588 static const MCOperandInfo OperandInfo276[] = { { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
5588 static const MCOperandInfo OperandInfo276[] = { { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
5676 static const MCOperandInfo OperandInfo364[] = { { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
5677 static const MCOperandInfo OperandInfo365[] = { { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_MEMORY, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
5677 static const MCOperandInfo OperandInfo365[] = { { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_MEMORY, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
5678 static const MCOperandInfo OperandInfo366[] = { { ARM::VCCRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
5679 static const MCOperandInfo OperandInfo367[] = { { ARM::VCCRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_MEMORY, ((1 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
5679 static const MCOperandInfo OperandInfo367[] = { { ARM::VCCRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_MEMORY, ((1 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
5751 static const MCOperandInfo OperandInfo439[] = { { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::VCCRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_MEMORY, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
5751 static const MCOperandInfo OperandInfo439[] = { { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::VCCRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_MEMORY, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
5762 static const MCOperandInfo OperandInfo450[] = { { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::OptionalDef), MCOI::OPERAND_UNKNOWN, 0 }, };
5762 static const MCOperandInfo OperandInfo450[] = { { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::OptionalDef), MCOI::OPERAND_UNKNOWN, 0 }, };
5763 static const MCOperandInfo OperandInfo451[] = { { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
5764 static const MCOperandInfo OperandInfo452[] = { { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::OptionalDef), MCOI::OPERAND_UNKNOWN, 0 }, };
5764 static const MCOperandInfo OperandInfo452[] = { { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::OptionalDef), MCOI::OPERAND_UNKNOWN, 0 }, };
5765 static const MCOperandInfo OperandInfo453[] = { { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::OptionalDef), MCOI::OPERAND_UNKNOWN, 0 }, };
5765 static const MCOperandInfo OperandInfo453[] = { { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::OptionalDef), MCOI::OPERAND_UNKNOWN, 0 }, };
5772 static const MCOperandInfo OperandInfo460[] = { { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
5773 static const MCOperandInfo OperandInfo461[] = { { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
5779 static const MCOperandInfo OperandInfo467[] = { { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
5779 static const MCOperandInfo OperandInfo467[] = { { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
5782 static const MCOperandInfo OperandInfo470[] = { { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
5783 static const MCOperandInfo OperandInfo471[] = { { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
5787 static const MCOperandInfo OperandInfo475[] = { { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::OptionalDef), MCOI::OPERAND_UNKNOWN, 0 }, };
5787 static const MCOperandInfo OperandInfo475[] = { { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::OptionalDef), MCOI::OPERAND_UNKNOWN, 0 }, };
5795 static const MCOperandInfo OperandInfo483[] = { { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
5802 static const MCOperandInfo OperandInfo490[] = { { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, (1 << MCOI::EARLY_CLOBBER) }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
5803 static const MCOperandInfo OperandInfo491[] = { { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
5805 static const MCOperandInfo OperandInfo493[] = { { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, (1 << MCOI::EARLY_CLOBBER) }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
5806 static const MCOperandInfo OperandInfo494[] = { { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, (1 << MCOI::EARLY_CLOBBER) }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
5806 static const MCOperandInfo OperandInfo494[] = { { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, (1 << MCOI::EARLY_CLOBBER) }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
5808 static const MCOperandInfo OperandInfo496[] = { { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
5819 static const MCOperandInfo OperandInfo507[] = { { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
gen/lib/Target/ARM/ARMGenRegisterBank.inc 62 (1u << (ARM::GPRnopcRegClassID - 0)) |
gen/lib/Target/ARM/ARMGenRegisterInfo.inc 2899 { GPRnopc, GPRnopcBits, 2305, 15, sizeof(GPRnopcBits), ARM::GPRnopcRegClassID, 1, true },
5998 const MCRegisterClass &MCR = ARMMCRegisterClasses[ARM::GPRnopcRegClassID];
6642 &ARMMCRegisterClasses[GPRnopcRegClassID],
lib/Target/ARM/ARMRegisterBankInfo.cpp 153 assert(RBGPR.covers(*TRI.getRegClass(ARM::GPRnopcRegClassID)) &&
182 case GPRnopcRegClassID:
lib/Target/ARM/AsmParser/ARMAsmParser.cpp 1393 if (!ARMMCRegisterClasses[ARM::GPRnopcRegClassID].contains(
1703 !ARMMCRegisterClasses[ARM::GPRnopcRegClassID].contains(
1765 if (!ARMMCRegisterClasses[ARM::GPRnopcRegClassID].contains(