reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced

References

gen/lib/Target/ARM/ARMGenRegisterBank.inc

   95 RegisterBank GPRRegBank(/* ID */ ARM::GPRRegBankID, /* Name */ "GPRB", /* Size */ 32, /* CoveredRegClasses */ GPRRegBankCoverageData, /* NumRegClasses */ 122);

lib/Target/ARM/ARMInstructionSelector.cpp

  192   assert((RegBank->getID() == ARM::GPRRegBankID ||
  247          RBI.getRegBank(VReg1, MRI, TRI)->getID() == ARM::GPRRegBankID &&
  252          RBI.getRegBank(VReg2, MRI, TRI)->getID() == ARM::GPRRegBankID &&
  274          RBI.getRegBank(VReg0, MRI, TRI)->getID() == ARM::GPRRegBankID &&
  279          RBI.getRegBank(VReg1, MRI, TRI)->getID() == ARM::GPRRegBankID &&
  359   if (RegBank == ARM::GPRRegBankID) {
  531   if (!validReg(MRI, ResReg, 1, ARM::GPRRegBankID))
  774   assert(validReg(MRI, CondReg, 1, ARM::GPRRegBankID) &&
  788   assert(validOpRegPair(MRI, ResReg, TrueReg, 32, ARM::GPRRegBankID) &&
  789          validOpRegPair(MRI, TrueReg, FalseReg, 32, ARM::GPRRegBankID) &&
  925       assert(DstRegBank.getID() == ARM::GPRRegBankID &&
  951     if (SrcRegBank.getID() != ARM::GPRRegBankID) {
 1022     if (SrcRegBank.getID() != ARM::GPRRegBankID) {
 1035                         Opcodes.MOVCCi, ARM::GPRRegBankID, 32);
 1134     if (!validReg(MRI, I.getOperand(0).getReg(), 1, ARM::GPRRegBankID)) {

lib/Target/ARM/ARMRegisterBankInfo.cpp

   57       checkPartMapping(PartMappings[PMI_GPR - PMI_Min], 0, 32, GPRRegBankID) &&
  144   const RegisterBank &RBGPR = getRegBank(ARM::GPRRegBankID);
  195     return getRegBank(ARM::GPRRegBankID);