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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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References
gen/lib/Target/ARM/ARMGenInstrInfo.inc 6044 { 211, 5, 1, 4, 419, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo56, -1 ,nullptr }, // Inst #211 = LDMIA_RET
6355 { 522, 5, 1, 4, 1007, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo56, -1 ,nullptr }, // Inst #522 = t2LDMIA_RET
6497 { 664, 5, 1, 4, 848, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x8b64ULL, nullptr, nullptr, OperandInfo56, -1 ,nullptr }, // Inst #664 = FLDMXDB_UPD
6499 { 666, 5, 1, 4, 848, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x8b64ULL, nullptr, nullptr, OperandInfo56, -1 ,nullptr }, // Inst #666 = FLDMXIA_UPD
6501 { 668, 5, 1, 4, 848, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x8b64ULL, nullptr, nullptr, OperandInfo56, -1 ,nullptr }, // Inst #668 = FSTMXDB_UPD
6503 { 670, 5, 1, 4, 848, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x8b64ULL, nullptr, nullptr, OperandInfo56, -1 ,nullptr }, // Inst #670 = FSTMXIA_UPD
6532 { 699, 5, 1, 4, 418, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::VariadicOpsAreDefs), 0x564ULL, nullptr, nullptr, OperandInfo56, -1 ,&getARMLoadDeprecationInfo }, // Inst #699 = LDMDA_UPD
6534 { 701, 5, 1, 4, 418, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::VariadicOpsAreDefs), 0x564ULL, nullptr, nullptr, OperandInfo56, -1 ,&getARMLoadDeprecationInfo }, // Inst #701 = LDMDB_UPD
6536 { 703, 5, 1, 4, 418, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::VariadicOpsAreDefs), 0x564ULL, nullptr, nullptr, OperandInfo56, -1 ,&getARMLoadDeprecationInfo }, // Inst #703 = LDMIA_UPD
6538 { 705, 5, 1, 4, 418, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::VariadicOpsAreDefs), 0x564ULL, nullptr, nullptr, OperandInfo56, -1 ,&getARMLoadDeprecationInfo }, // Inst #705 = LDMIB_UPD
7615 { 1782, 5, 1, 4, 448, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x564ULL, nullptr, nullptr, OperandInfo56, -1 ,&getARMStoreDeprecationInfo }, // Inst #1782 = STMDA_UPD
7617 { 1784, 5, 1, 4, 448, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x564ULL, nullptr, nullptr, OperandInfo56, -1 ,&getARMStoreDeprecationInfo }, // Inst #1784 = STMDB_UPD
7619 { 1786, 5, 1, 4, 448, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x564ULL, nullptr, nullptr, OperandInfo56, -1 ,&getARMStoreDeprecationInfo }, // Inst #1786 = STMIA_UPD
7621 { 1788, 5, 1, 4, 448, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x564ULL, nullptr, nullptr, OperandInfo56, -1 ,&getARMStoreDeprecationInfo }, // Inst #1788 = STMIB_UPD
8460 { 2627, 5, 1, 4, 592, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x8be4ULL, nullptr, nullptr, OperandInfo56, -1 ,nullptr }, // Inst #2627 = VLDMDDB_UPD
8462 { 2629, 5, 1, 4, 592, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x8be4ULL, nullptr, nullptr, OperandInfo56, -1 ,nullptr }, // Inst #2629 = VLDMDIA_UPD
8464 { 2631, 5, 1, 4, 592, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x18be4ULL, nullptr, nullptr, OperandInfo56, -1 ,nullptr }, // Inst #2631 = VLDMSDB_UPD
8466 { 2633, 5, 1, 4, 592, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x18be4ULL, nullptr, nullptr, OperandInfo56, -1 ,nullptr }, // Inst #2633 = VLDMSIA_UPD
9425 { 3592, 5, 1, 4, 594, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x8be4ULL, nullptr, nullptr, OperandInfo56, -1 ,nullptr }, // Inst #3592 = VSTMDDB_UPD
9427 { 3594, 5, 1, 4, 594, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x8be4ULL, nullptr, nullptr, OperandInfo56, -1 ,nullptr }, // Inst #3594 = VSTMDIA_UPD
9429 { 3596, 5, 1, 4, 961, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x18be4ULL, nullptr, nullptr, OperandInfo56, -1 ,nullptr }, // Inst #3596 = VSTMSDB_UPD
9431 { 3598, 5, 1, 4, 961, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x18be4ULL, nullptr, nullptr, OperandInfo56, -1 ,nullptr }, // Inst #3598 = VSTMSIA_UPD
9557 { 3724, 5, 1, 4, 418, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x564ULL, nullptr, nullptr, OperandInfo56, -1 ,nullptr }, // Inst #3724 = sysLDMDA_UPD
9559 { 3726, 5, 1, 4, 418, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x564ULL, nullptr, nullptr, OperandInfo56, -1 ,nullptr }, // Inst #3726 = sysLDMDB_UPD
9561 { 3728, 5, 1, 4, 418, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x564ULL, nullptr, nullptr, OperandInfo56, -1 ,nullptr }, // Inst #3728 = sysLDMIA_UPD
9563 { 3730, 5, 1, 4, 418, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x564ULL, nullptr, nullptr, OperandInfo56, -1 ,nullptr }, // Inst #3730 = sysLDMIB_UPD
9565 { 3732, 5, 1, 4, 448, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x564ULL, nullptr, nullptr, OperandInfo56, -1 ,nullptr }, // Inst #3732 = sysSTMDA_UPD
9567 { 3734, 5, 1, 4, 448, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x564ULL, nullptr, nullptr, OperandInfo56, -1 ,nullptr }, // Inst #3734 = sysSTMDB_UPD
9569 { 3736, 5, 1, 4, 448, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x564ULL, nullptr, nullptr, OperandInfo56, -1 ,nullptr }, // Inst #3736 = sysSTMIA_UPD
9571 { 3738, 5, 1, 4, 448, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x564ULL, nullptr, nullptr, OperandInfo56, -1 ,nullptr }, // Inst #3738 = sysSTMIB_UPD
9662 { 3829, 5, 1, 4, 1008, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::VariadicOpsAreDefs), 0xc80ULL, nullptr, nullptr, OperandInfo56, -1 ,nullptr }, // Inst #3829 = t2LDMDB_UPD
9664 { 3831, 5, 1, 4, 1008, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::VariadicOpsAreDefs), 0xc80ULL, nullptr, nullptr, OperandInfo56, -1 ,nullptr }, // Inst #3831 = t2LDMIA_UPD
9871 { 4038, 5, 1, 4, 1015, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xc80ULL, nullptr, nullptr, OperandInfo56, -1 ,nullptr }, // Inst #4038 = t2STMDB_UPD
9873 { 4040, 5, 1, 4, 1015, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xc80ULL, nullptr, nullptr, OperandInfo56, -1 ,nullptr }, // Inst #4040 = t2STMIA_UPD