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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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References
gen/lib/Target/ARM/ARMGenInstrInfo.inc 9736 { 3903, 5, 1, 4, 372, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0xc80ULL, nullptr, nullptr, OperandInfo478, -1 ,nullptr }, // Inst #3903 = t2MUL
9759 { 3926, 5, 1, 4, 887, 0|(1ULL<<MCID::Predicable), 0xc80ULL, nullptr, nullptr, OperandInfo478, -1 ,nullptr }, // Inst #3926 = t2QADD
9760 { 3927, 5, 1, 4, 887, 0|(1ULL<<MCID::Predicable), 0xc80ULL, nullptr, nullptr, OperandInfo478, -1 ,nullptr }, // Inst #3927 = t2QADD16
9761 { 3928, 5, 1, 4, 887, 0|(1ULL<<MCID::Predicable), 0xc80ULL, nullptr, nullptr, OperandInfo478, -1 ,nullptr }, // Inst #3928 = t2QADD8
9762 { 3929, 5, 1, 4, 889, 0|(1ULL<<MCID::Predicable), 0xc80ULL, nullptr, nullptr, OperandInfo478, -1 ,nullptr }, // Inst #3929 = t2QASX
9763 { 3930, 5, 1, 4, 361, 0|(1ULL<<MCID::Predicable), 0xc80ULL, nullptr, nullptr, OperandInfo478, -1 ,nullptr }, // Inst #3930 = t2QDADD
9764 { 3931, 5, 1, 4, 361, 0|(1ULL<<MCID::Predicable), 0xc80ULL, nullptr, nullptr, OperandInfo478, -1 ,nullptr }, // Inst #3931 = t2QDSUB
9765 { 3932, 5, 1, 4, 889, 0|(1ULL<<MCID::Predicable), 0xc80ULL, nullptr, nullptr, OperandInfo478, -1 ,nullptr }, // Inst #3932 = t2QSAX
9766 { 3933, 5, 1, 4, 887, 0|(1ULL<<MCID::Predicable), 0xc80ULL, nullptr, nullptr, OperandInfo478, -1 ,nullptr }, // Inst #3933 = t2QSUB
9767 { 3934, 5, 1, 4, 887, 0|(1ULL<<MCID::Predicable), 0xc80ULL, nullptr, nullptr, OperandInfo478, -1 ,nullptr }, // Inst #3934 = t2QSUB16
9768 { 3935, 5, 1, 4, 887, 0|(1ULL<<MCID::Predicable), 0xc80ULL, nullptr, nullptr, OperandInfo478, -1 ,nullptr }, // Inst #3935 = t2QSUB8
9783 { 3950, 5, 1, 4, 883, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo478, -1 ,nullptr }, // Inst #3950 = t2SADD16
9784 { 3951, 5, 1, 4, 883, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo478, -1 ,nullptr }, // Inst #3951 = t2SADD8
9785 { 3952, 5, 1, 4, 364, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo478, -1 ,nullptr }, // Inst #3952 = t2SASX
9791 { 3958, 5, 1, 4, 682, 0|(1ULL<<MCID::Predicable), 0xc80ULL, nullptr, nullptr, OperandInfo478, -1 ,nullptr }, // Inst #3958 = t2SDIV
9795 { 3962, 5, 1, 4, 885, 0|(1ULL<<MCID::Predicable), 0xc80ULL, nullptr, nullptr, OperandInfo478, -1 ,nullptr }, // Inst #3962 = t2SHADD16
9796 { 3963, 5, 1, 4, 885, 0|(1ULL<<MCID::Predicable), 0xc80ULL, nullptr, nullptr, OperandInfo478, -1 ,nullptr }, // Inst #3963 = t2SHADD8
9797 { 3964, 5, 1, 4, 367, 0|(1ULL<<MCID::Predicable), 0xc80ULL, nullptr, nullptr, OperandInfo478, -1 ,nullptr }, // Inst #3964 = t2SHASX
9798 { 3965, 5, 1, 4, 367, 0|(1ULL<<MCID::Predicable), 0xc80ULL, nullptr, nullptr, OperandInfo478, -1 ,nullptr }, // Inst #3965 = t2SHSAX
9799 { 3966, 5, 1, 4, 885, 0|(1ULL<<MCID::Predicable), 0xc80ULL, nullptr, nullptr, OperandInfo478, -1 ,nullptr }, // Inst #3966 = t2SHSUB16
9800 { 3967, 5, 1, 4, 885, 0|(1ULL<<MCID::Predicable), 0xc80ULL, nullptr, nullptr, OperandInfo478, -1 ,nullptr }, // Inst #3967 = t2SHSUB8
9825 { 3992, 5, 1, 4, 372, 0|(1ULL<<MCID::Predicable), 0xc80ULL, nullptr, nullptr, OperandInfo478, -1 ,nullptr }, // Inst #3992 = t2SMMUL
9826 { 3993, 5, 1, 4, 372, 0|(1ULL<<MCID::Predicable), 0xc80ULL, nullptr, nullptr, OperandInfo478, -1 ,nullptr }, // Inst #3993 = t2SMMULR
9827 { 3994, 5, 1, 4, 376, 0|(1ULL<<MCID::Predicable), 0xc80ULL, nullptr, nullptr, OperandInfo478, -1 ,nullptr }, // Inst #3994 = t2SMUAD
9828 { 3995, 5, 1, 4, 376, 0|(1ULL<<MCID::Predicable), 0xc80ULL, nullptr, nullptr, OperandInfo478, -1 ,nullptr }, // Inst #3995 = t2SMUADX
9829 { 3996, 5, 1, 4, 373, 0|(1ULL<<MCID::Predicable), 0xc80ULL, nullptr, nullptr, OperandInfo478, -1 ,nullptr }, // Inst #3996 = t2SMULBB
9830 { 3997, 5, 1, 4, 373, 0|(1ULL<<MCID::Predicable), 0xc80ULL, nullptr, nullptr, OperandInfo478, -1 ,nullptr }, // Inst #3997 = t2SMULBT
9832 { 3999, 5, 1, 4, 373, 0|(1ULL<<MCID::Predicable), 0xc80ULL, nullptr, nullptr, OperandInfo478, -1 ,nullptr }, // Inst #3999 = t2SMULTB
9833 { 4000, 5, 1, 4, 373, 0|(1ULL<<MCID::Predicable), 0xc80ULL, nullptr, nullptr, OperandInfo478, -1 ,nullptr }, // Inst #4000 = t2SMULTT
9834 { 4001, 5, 1, 4, 373, 0|(1ULL<<MCID::Predicable), 0xc80ULL, nullptr, nullptr, OperandInfo478, -1 ,nullptr }, // Inst #4001 = t2SMULWB
9835 { 4002, 5, 1, 4, 373, 0|(1ULL<<MCID::Predicable), 0xc80ULL, nullptr, nullptr, OperandInfo478, -1 ,nullptr }, // Inst #4002 = t2SMULWT
9836 { 4003, 5, 1, 4, 374, 0|(1ULL<<MCID::Predicable), 0xc80ULL, nullptr, nullptr, OperandInfo478, -1 ,nullptr }, // Inst #4003 = t2SMUSD
9837 { 4004, 5, 1, 4, 374, 0|(1ULL<<MCID::Predicable), 0xc80ULL, nullptr, nullptr, OperandInfo478, -1 ,nullptr }, // Inst #4004 = t2SMUSDX
9844 { 4011, 5, 1, 4, 364, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo478, -1 ,nullptr }, // Inst #4011 = t2SSAX
9845 { 4012, 5, 1, 4, 883, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo478, -1 ,nullptr }, // Inst #4012 = t2SSUB16
9846 { 4013, 5, 1, 4, 883, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo478, -1 ,nullptr }, // Inst #4013 = t2SSUB8
9923 { 4090, 5, 1, 4, 883, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo478, -1 ,nullptr }, // Inst #4090 = t2UADD16
9924 { 4091, 5, 1, 4, 883, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo478, -1 ,nullptr }, // Inst #4091 = t2UADD8
9925 { 4092, 5, 1, 4, 364, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo478, -1 ,nullptr }, // Inst #4092 = t2UASX
9928 { 4095, 5, 1, 4, 682, 0|(1ULL<<MCID::Predicable), 0xc80ULL, nullptr, nullptr, OperandInfo478, -1 ,nullptr }, // Inst #4095 = t2UDIV
9929 { 4096, 5, 1, 4, 885, 0|(1ULL<<MCID::Predicable), 0xc80ULL, nullptr, nullptr, OperandInfo478, -1 ,nullptr }, // Inst #4096 = t2UHADD16
9930 { 4097, 5, 1, 4, 885, 0|(1ULL<<MCID::Predicable), 0xc80ULL, nullptr, nullptr, OperandInfo478, -1 ,nullptr }, // Inst #4097 = t2UHADD8
9931 { 4098, 5, 1, 4, 367, 0|(1ULL<<MCID::Predicable), 0xc80ULL, nullptr, nullptr, OperandInfo478, -1 ,nullptr }, // Inst #4098 = t2UHASX
9932 { 4099, 5, 1, 4, 367, 0|(1ULL<<MCID::Predicable), 0xc80ULL, nullptr, nullptr, OperandInfo478, -1 ,nullptr }, // Inst #4099 = t2UHSAX
9933 { 4100, 5, 1, 4, 885, 0|(1ULL<<MCID::Predicable), 0xc80ULL, nullptr, nullptr, OperandInfo478, -1 ,nullptr }, // Inst #4100 = t2UHSUB16
9934 { 4101, 5, 1, 4, 885, 0|(1ULL<<MCID::Predicable), 0xc80ULL, nullptr, nullptr, OperandInfo478, -1 ,nullptr }, // Inst #4101 = t2UHSUB8
9938 { 4105, 5, 1, 4, 887, 0|(1ULL<<MCID::Predicable), 0xc80ULL, nullptr, nullptr, OperandInfo478, -1 ,nullptr }, // Inst #4105 = t2UQADD16
9939 { 4106, 5, 1, 4, 887, 0|(1ULL<<MCID::Predicable), 0xc80ULL, nullptr, nullptr, OperandInfo478, -1 ,nullptr }, // Inst #4106 = t2UQADD8
9940 { 4107, 5, 1, 4, 889, 0|(1ULL<<MCID::Predicable), 0xc80ULL, nullptr, nullptr, OperandInfo478, -1 ,nullptr }, // Inst #4107 = t2UQASX
9941 { 4108, 5, 1, 4, 889, 0|(1ULL<<MCID::Predicable), 0xc80ULL, nullptr, nullptr, OperandInfo478, -1 ,nullptr }, // Inst #4108 = t2UQSAX
9942 { 4109, 5, 1, 4, 887, 0|(1ULL<<MCID::Predicable), 0xc80ULL, nullptr, nullptr, OperandInfo478, -1 ,nullptr }, // Inst #4109 = t2UQSUB16
9943 { 4110, 5, 1, 4, 887, 0|(1ULL<<MCID::Predicable), 0xc80ULL, nullptr, nullptr, OperandInfo478, -1 ,nullptr }, // Inst #4110 = t2UQSUB8
9944 { 4111, 5, 1, 4, 681, 0|(1ULL<<MCID::Predicable), 0xc80ULL, nullptr, nullptr, OperandInfo478, -1 ,nullptr }, // Inst #4111 = t2USAD8
9948 { 4115, 5, 1, 4, 364, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo478, -1 ,nullptr }, // Inst #4115 = t2USAX
9949 { 4116, 5, 1, 4, 883, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo478, -1 ,nullptr }, // Inst #4116 = t2USUB16
9950 { 4117, 5, 1, 4, 883, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo478, -1 ,nullptr }, // Inst #4117 = t2USUB8