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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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References
gen/lib/Target/ARM/ARMGenInstrInfo.inc 9573 { 3740, 6, 1, 4, 697, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasOptionalDef)|(1ULL<<MCID::HasPostISelHook), 0xc80ULL, ImplicitList1, ImplicitList1, OperandInfo448, -1 ,nullptr }, // Inst #3740 = t2ADCrr
9581 { 3748, 6, 1, 4, 699, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasOptionalDef), 0xc80ULL, nullptr, nullptr, OperandInfo448, -1 ,nullptr }, // Inst #3748 = t2ANDrr
9584 { 3751, 6, 1, 4, 879, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0xc80ULL, nullptr, nullptr, OperandInfo448, -1 ,nullptr }, // Inst #3751 = t2ASRrr
9594 { 3761, 6, 1, 4, 699, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0xc80ULL, nullptr, nullptr, OperandInfo448, -1 ,nullptr }, // Inst #3761 = t2BICrr
9630 { 3797, 6, 1, 4, 699, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasOptionalDef), 0xc80ULL, nullptr, nullptr, OperandInfo448, -1 ,nullptr }, // Inst #3797 = t2EORrr
9710 { 3877, 6, 1, 4, 879, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0xc80ULL, nullptr, nullptr, OperandInfo448, -1 ,nullptr }, // Inst #3877 = t2LSLrr
9712 { 3879, 6, 1, 4, 879, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0xc80ULL, nullptr, nullptr, OperandInfo448, -1 ,nullptr }, // Inst #3879 = t2LSRrr
9741 { 3908, 6, 1, 4, 43, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0xc80ULL, nullptr, nullptr, OperandInfo448, -1 ,nullptr }, // Inst #3908 = t2ORNrr
9744 { 3911, 6, 1, 4, 43, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasOptionalDef), 0xc80ULL, nullptr, nullptr, OperandInfo448, -1 ,nullptr }, // Inst #3911 = t2ORRrr
9778 { 3945, 6, 1, 4, 879, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0xc80ULL, nullptr, nullptr, OperandInfo448, -1 ,nullptr }, // Inst #3945 = t2RORrr
9781 { 3948, 6, 1, 4, 2, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo448, -1 ,nullptr }, // Inst #3948 = t2RSBrr
9788 { 3955, 6, 1, 4, 697, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef)|(1ULL<<MCID::HasPostISelHook), 0xc80ULL, ImplicitList1, ImplicitList1, OperandInfo448, -1 ,nullptr }, // Inst #3955 = t2SBCrr